Fabrication method of semiconductor structure

Abstract

A method for manufacturing a semiconductor structure comprises the following steps that firstly, a first grating laminated structure is formed on a PMOS transistor area of a semiconductor substrate, a second grating laminated structure is formed in an NMOS transistor area of the semiconductor substrate, the first grating laminated structure and the second grating laminated structure respectively comprise a grating dieletric layer, a grid electrode layer, a first hard mask and a second hard mask, and side walls are formed in the opposite sides of the first grating laminated structure and the second grating laminated structure; secondly, an SiGe stress source layer is formed in an area, where PMOS transistor source leakage is formed, of the substrate, and then each second hard mask is removed; thirdly, silicide is formed in the PMOS transistor source leakage area and the NMOS transistor source leakage area, and then the residual metal contacted material layer and each first hard mask layer are removed synchronously; fourthly, the side walls of the two sides of the first grating laminated structure and the second grating laminated structure are etched, and then the side walls become thin. In the process of manufacturing, the occurrences that silicide on the PMOS transistor source leakage area and the NMOS transistor source leakage area is excessively etched due to the fact that the thicknesses of each hard mask above the grating layer are not equal before the side walls are etched, or the height of a transistor grating is lowered due to the fact that each hard mask is excessively grinded in the subsequent chemical mechanical grinding technique cannot happen.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a method for manufacturing a semiconductor structure. Background technique [0002] A common trend in modern integrated circuit manufacturing is to produce transistors with very small feature sizes, and most transistors include a stack of gate dielectric layers made of silicon oxide (or silicon oxynitride, etc.) and gates made of polysilicon. layer structure. As the size of transistors becomes smaller and smaller, there are many problems in transistors, such as gate current leakage, polysilicon depletion, boron penetration effect, etc., which affect the further development of integrated circuits. In order to solve the above problems, a new type of transistor has been studied: it replaces the material of the gate dielectric layer from silicon oxide with a high-K dielectric layer (K ​​here refers to a dielectric constant), and changes the material of the gate from ...

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Problems solved by technology

[0015] like Figure 5 As shown, in the process of thinning the sidewall 16, the etchant or etching gas will simultaneously etch the silicide 20 above the source and drain of the PMOS transistor and the NMOS transistor, and combined with image 3 As shown, the thickness of the hard mask 15 in the second gate stack structure 12 is greater than the thickness of the hard mask 15 in the first gate stack structure 11. The hard mask 15 in 12 is completely removed (the hard mask 15 in the first gate stack structure 11 will also be completely removed at this time), then the etching time required for the hard mask 15 will be lengthened, and the transistor source and drain The etching time of the upper silicide 20 is also prolonged accordingly, resulting in excessive loss of silicide on the source and drain of the transistor, which affects the performance of the semiconductor structure; if the first gate stack structure is to be realized while thinning the sidewall 16 If the hard mask 15 in 11 is completely removed, the hard mask 15 in the second gate stack structure 12 will remain, as Image 6 As shown, in order to simplify the manufacturing process of the semiconductor structure at this time, it is hoped that Figure 7 The remaining hard mask 15 is removed during the shown chemical mechanical polishing (CMP) process. In order to ensure that the remaining hard mask 15 can be completely removed, the semiconductor structure is often over-polished, resulting in the first gate The gate layer 14 in the stacked structure 11 and the second gate stacked structure 12 is also ground to reduce its thickness, resulting in a reduction in the gate height of the PMOS transistor and the NMOS transistor, which affects the performance of the semiconductor structure

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