A high-speed decoding circuit based on data transmission

Abstract

The invention discloses a high-speed decoding circuit based on data transmission. The high-speed decoding circuit based mainly solves the problem that a circuit of an existing decoder is complex. A basic circuit of the high-speed decoding circuit is composed of 16 MOS transistors, S (1) and Sv (1), and S (0) and Sv (0) are two complementary high-low phase address selection signals, and the correct decoding function is achieved in a manner that correlated MOS transistors are controlled to be conducted or disconnected sequentially. The basic circuit of the high-speed decoding circuit is divided into an upper structure and a lower structure, M0-M3 NMOS tubes are introduced into the second structure, and therefore voltage swing losses of the signals on a transmission path are reduced effectively. The high-speed decoding circuit has the advantages of being simple in structure, high in speed, small in area, low in power consumption, and the like, in addition, the advantages can be more obvious along with the increase of the number of decoding addresses, and the high-speed decoding circuit can be used for storer address decoding and high-speed data selection circuits.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and relates to a decoding circuit, in particular to a high-speed decoding circuit based on data transmission. Background technique [0002] Decoder is an important logic module unit of data selection circuit, memory and other circuits. With the advancement of integrated circuit design technology and process feature size, the scale of the system on a chip is getting bigger and bigger, and the speed is also increasing. For multi-channel data selection circuits and large-capacity storage circuits, a multi-bit address decoder is essential. However, the traditional multi-bit address decoder structure has disadvantages such as complex circuits, slow speed, and large area. figure 1 What is shown is a traditional 3-8-wire decoder circuit. Its main structure is composed of 8 "3-input NAND gates", including 24 NMOS transistors and 24 PMOS transistors. On the one hand, the circuit structure is ...

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Problems solved by technology

For multi-channel data selection circuits and large-capacity storage circuits, decoders with multi-bit addresses are essential. However, the traditional structure of multi-bit address decoders has disadvantages such as complex circuits, slow speed, and large area.

figure 1 What is shown is a traditional 3-8-wire decoder circuit. Its main structure is composed of 8 "3-input NAND gates", including 24 NMOS transistors and 24 PMOS transistors. On the one hand, the circuit structure is relatively complicated and the layout The area is large and the process cost is high; on the other hand, there are 6 transistors (4 PMOS transistors and 2 NMOS transistors) directly connected to the output terminal of each NAND gate, resulting in large parasitic capacitance at the output terminal and slow circuit speed. high

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