Insulated gate bipolar transistor and manufacturing method thereof
A bipolar transistor, insulated gate technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as limited effect, reduced IGBT conductance modulation characteristics, increased forward voltage drop, etc., to achieve VCE reduction , Improve conductance modulation characteristics, the effect of flexible position
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Embodiment 1
[0077] Such as Figures 2A to 2F As shown, the present invention provides a kind of preparation method of insulated gate bipolar transistor, and this method comprises the following steps at least:
[0078] First perform step 1), providing a heavily doped first conductivity type semiconductor substrate 11, the semiconductor substrate 11 is used as a collector region, and forming a lightly doped second conductivity type epitaxial layer 122 on the semiconductor substrate 11 .
[0079] It should be noted that before forming the lightly doped second conductivity type epitaxial layer 122, it also includes forming a heavily doped second conductivity type buffer layer 121 on the semiconductor substrate 11, so as to prevent depletion when blocking voltage. layer reaches the semiconductor substrate 11 , and the buffer layer 121 is used to control the ability of the semiconductor substrate 11 to inject minority carriers into the buffer, that is, to control the injection efficiency of th...
Embodiment 2
[0092] Such as Figures 3A to 3F As shown, the present invention provides a kind of preparation method of insulated gate bipolar transistor, and this method comprises the following steps at least:
[0093] First perform the same step 1) as in Embodiment 1, that is, in Embodiment 2, a heavily doped N-type (N+) buffer is first formed on a heavily doped P-type (P+) semiconductor substrate 21 as a collector region. layer 221, and then form a lightly doped N-type (N-) epitaxial layer 222 on the buffer layer 221, wherein the P+ semiconductor substrate 21, N+ buffer layer 221, and N- epitaxial layer 222 are silicon. Then execute step 2).
[0094] In step 2) of the second embodiment, the insulating buried layer 28 under the body region 25 prepared subsequently, the gate region 23 and the isolation structure 24 located on the epitaxial layer 222, and the The emission region 26 and the body region 25 in 222 specifically include the following steps:
[0095] In step 2-1), see Figure...
Embodiment 3
[0105] Such as Figure 4 As shown, the present invention provides an insulated gate bipolar transistor, which at least includes a collector 392, a semiconductor substrate 31, a drift region 323, a body region 35, an emitter region 36, a gate region 33, an isolation structure 34, an insulating buried layer 38, Emitter 391 .
[0106] It should be noted that, in the third embodiment, the first conductivity type is P-type, and the second conductivity type is N-type.
[0107] The collector 392 is located under the semiconductor substrate 31 of the insulated gate bipolar transistor, and is used for power supply connection. In the third embodiment, the collector 392 is made of aluminum. In other embodiments, the collector 392 The material is copper or aluminum-copper alloy.
[0108] The semiconductor substrate 31 is heavily doped with the first conductivity type. In the third embodiment, it is a P+ semiconductor substrate 31 made of silicon material, which is located on the collect...
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