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Packaging-prior-to-etching type three-dimensional system-level chip-flipped packaging structure and process method thereof

A system-level chip and flip-chip packaging technology, which is applied in the manufacture of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc., can solve problems such as the inability to embed chips and limit the integration of packaging functions

Active Publication Date: 2013-11-20
江苏尊阳电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The purpose of the present invention is to overcome the above-mentioned shortcomings, and provide a three-dimensional system-in-package structure and process method for sealing first and then etching chips, which can solve the problem that traditional metal lead frames or multilayer circuit substrates cannot embed chips and passive components. The problem of packaging function integration and traditional organic substrates require thinner line width and narrower line-to-line spacing

Method used

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  • Packaging-prior-to-etching type three-dimensional system-level chip-flipped packaging structure and process method thereof
  • Packaging-prior-to-etching type three-dimensional system-level chip-flipped packaging structure and process method thereof
  • Packaging-prior-to-etching type three-dimensional system-level chip-flipped packaging structure and process method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0194] Embodiment 1, single-layer circuit single-chip flip-chip single-turn pin

[0195] see Figure 28 , is a structural schematic diagram of Embodiment 1 of the three-dimensional system-on-a-chip flip-chip packaging structure of the present invention, which includes a base island 1 and pins 2, and the front side of the base island 1 is formally mounted with a conductive or non-conductive adhesive material 3. There is a first chip 4, and a second chip 6 is flip-mounted on the backside of the base island 1 and the pin 2 through the underfill glue 5, and the front side of the first chip 4 and the front side of the pin 2 are connected by a metal wire 7. connection, a conductive pillar 8 is arranged on the front of the pin 2, the area around the base island 1, the area between the base island 1 and the pin 2, the area between the pin 2 and the pin 2, the base island 1 and the upper part of the pin 2, the base island 1 and the lower part of the pin 2, as well as the first chip 4,...

Embodiment 2

[0251] Embodiment 2, multi-turn single-chip flip chip + passive device + electrostatic discharge ring

[0252] see Figure 29 , is a structural schematic diagram of Embodiment 2 of the three-dimensional system-on-a-chip flip-chip packaging structure that is etched first and then sealed in the present invention. The difference between Embodiment 2 and Embodiment 1 is that the conductive pillar 8 has multiple turns, and the pin 2 The passive device 11 is bridged by a conductive adhesive substance between the pin 2, and an electrostatic discharge ring 14 is provided between the base island 1 and the pin 2, and the passive device 11 can be bridged to the pin 2 Between the back and the front of the pin 2, or between the back of the pin 2 and the back of the ESD ring 14, or between the back of the base island 1 and the back of the ESD ring 14.

Embodiment 3

[0253] Embodiment 3, single-turn multi-base island tiling multi-chip flip chip

[0254] see Figure 30 , is a structural schematic diagram of Embodiment 3 of the three-dimensional system-on-a-chip flip-chip package structure of the present invention, which is etched first and then sealed. The filler 5 is flip-chip mounted with a plurality of second chips 6 .

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Abstract

The invention relates to a packaging-prior-to-etching type three-dimensional system-level chip-flipped packaging structure and a process method thereof. The structure comprises a pad and pins, wherein a first chip is arranged on the front surface of the pad; second chips are flipped on the back surfaces of the pad and the pins through bottom filling adhesives; the front surfaces of the first chip and the pins are connected through metal wires; conductive columns are arranged on the front surfaces of the pins; molding compounds are encapsulated in the peripheral area of the pad, the areas between the pad and the pins and between each two pins, the upper areas of the pad and the pins, the lower areas of the pad and the pins, and the external areas of the first chip, the second chips, the metal wires and the conductive columns; and anti-oxidation layers are plated on the surfaces, exposed from the molding compounds, of the pins and the conductive columns. By virtue of the packaging-prior-to-etching type three-dimensional system-level chip-flipped packaging structure and the process method thereof, the problem of limitation of the functionality and application performance of a metal lead frame caused by difficulty in embedding of an object into a conventional metal lead frame can be solved.

Description

technical field [0001] The invention relates to a three-dimensional system-level chip flip-chip packaging structure and process method which are etched first and then sealed. It belongs to the technical field of semiconductor packaging. Background technique [0002] Traditional four-sided leadless metal lead frame package structure such as Figure 79 As shown, the main manufacturing process is to take metal sheets for chemical etching and metal plating to make a base island for carrying chips and a metal lead frame with inner and outer pins, and then perform one-sided chip loading and wire bonding on this basis. , encapsulation and other packaging processes. [0003] The traditional organic multilayer circuit substrate packaging structure such as Figure 80 As shown, the main process is to form a multi-layer circuit board by stacking the core material of the glass fiber board by accumulating materials, opening holes between the circuit layers by laser drilling, and then pl...

Claims

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Application Information

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IPC IPC(8): H01L21/48H01L21/56H01L23/495H01L23/31
CPCH01L2224/48091H01L2224/73204H01L2224/73265H01L2224/92247H01L2924/00014
Inventor 梁志忠梁新夫王亚琴王孙艳章春燕
Owner 江苏尊阳电子科技有限公司
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