Fine spacing laminated packaging structure containing copper pillar and packaging method

Abstract

The invention provides a fine spacing laminated packaging structure containing a copper pillar, which comprises a lower packaging body and an upper packaging body, wherein the lower packaging body comprises a lower substrate, and a first chip is installed at a chip packaging area of the upper surface of the lower substrate and is electrically connected with the lower substrate; a welding area of the upper surface of the lower substrate is provided with the copper pillar, and a first welding ball is arranged on the copper pillar; the first welding ball and the upper surface of the lower substrate are pre-packaged by a packaging material, and the top of the first welding ball shows the packaging material of the upper surface of the lower substrate; the upper packaging body comprises an upper substrate, and a second chip is installed at the upper surface of the upper substrate and is electrically connected with the upper substrate; a welding area of the lower surface of the upper substrate is provided with a second welding ball. The upper substrate and the lower substrate are mutually connected through the butting joint of the second welding ball and the first welding ball. The packaging structure adopts the copper pillar so that the ball diameter of the welding balls can be shortened, and therefore the purpose of fine spacing packaging is achieved. As the copper pillar is manufactured in a welding line way, the complex electroplating process is omitted. The fine spacing laminated packaging structure has the advantages of simplicity in manufacture, low cost and the like.

Description

technical field [0001] The invention relates to the field of integrated circuit packaging, in particular to a fine-pitch stacked packaging structure and packaging method including copper pillars. Background technique [0002] With the continuous advancement of microelectronics technology, the feature size of integrated circuits has been continuously reduced and the interconnection density has been continuously increased. At the same time, users' requirements for high performance and low power consumption continue to increase. In this case, the way to improve the performance by further reducing the line width of the interconnection is limited by the physical characteristics of the material and the equipment process, and the resistance-capacitance (RC) delay of the two-dimensional interconnection gradually becomes the limit to improve the performance of the semiconductor chip. bottleneck. [0003] Chip stacking is one of the main ways to increase the density of electronic pa...

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Problems solved by technology

[0004] In the patent application document with the publication number CN102325431A, it is recorded that Shennan Circuits Co., Ltd. (hereinafter referred to as Shennan Company) makes copper pillars on the substrate by electroplating, so that the pitch between the substrate pads can be saved, but the electroplating The cost is too high, so it is necessary to propose a new copper column manufacturing method to solve the problem of excessive cost of the existing electroplating method

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