Method for manufacturing solar cell with local back surface field passivation
A solar cell and partial back field technology, applied in the direction of final product manufacturing, sustainable manufacturing/processing, circuits, etc., can solve the problems of small production capacity, difficult mask realization, unsuitable for mass production, etc., to reduce manufacturing costs and The effect of process time and process cost reduction
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Embodiment 1
[0037] Step 1: Texture making and polishing, forming a textured surface on the front of the 156mm*156mm silicon wafer, and polishing on the back;
[0038] For multi-crystalline silicon wafers, the conventional acid texturing method (HF acid + HNO3 acid) is first used to texturize both sides or one side of the silicon wafer; then one side is polished. :HNO3:glacial acetic acid=3:5:3 volume ratio) for polishing.
[0039] Step 2, back coating, using SiO2 or AL2O3 method for back coating;
[0040] That is, use PECVD equipment to deposit SiO2 and SiNx laminated films on the back of the silicon wafer, with a total thickness of 80-150nm; or use atomic layer deposition equipment or PECVD equipment to deposit Al2O3 and SiNx laminated films on the back of the silicon wafer, with a total thickness of Between 80-150nm.
[0041] Step 3, front diffusion, using a diffusion process to form a PN junction;
[0042] In a high-temperature diffusion furnace (between 760°C and 850°C), POCl3, O2,...
Embodiment 2
[0052] Step 1: Texture making, forming a textured surface on one or both sides of a 156mm*156mm silicon wafer;
[0053] For polycrystalline silicon wafers, the conventional acid texturing (HF acid + HNO3 acid) process is first used to texturize both sides or one side of the silicon wafer.
[0054] Step 2, front diffusion, using the diffusion method to form a PN junction;
[0055] In a high-temperature diffusion furnace (between 760°C and 850°C), POCl3, O2, and N2 gases are passed through for high-temperature diffusion to form a PN junction.
[0056] Step 3, remove edge knots and back polishing, remove edge knots and perform back polishing at the same time;
[0057] The single-side polishing process plan is: the upper surface of the silicon wafer is protected by a water film, and the lower surface is polished with a strong acid (HF:HNO3:glacial acetic acid = 3:5:3 volume ratio) to remove the edge knot.
[0058] Step 4, back coating, using SiO2 or AL2O3 method for back coating...
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