Groove Formation Method

Abstract

The invention discloses a method for forming a groove. The method comprises the steps that a substrate is provided, wherein a dielectric layer and a mask layer are formed on the substrate, a plurality of through holes are formed in the dielectric layer and the mask layer, and optical approximate layers are formed on the mask layer and in the through holes; a dry etching process is executed many times to remove part of the optical approximate layer on the mask layer, and the height difference of the remaining optical approximate layers in the through holes of all areas on the substrate is made to be smaller than a preset value. Through the method, the defects of a copper hill (hill-lock) are reduced, and meanwhile device electromigration defects can be effectively restrained.

Description

technical field [0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a method for forming a groove. Background technique [0002] At present, in the field of semiconductor integrated circuit manufacturing, after the semiconductor device layer is formed, in the backend of line (BEOL) process of the semiconductor device, it is necessary to form a metal interconnection layer on the semiconductor device layer, and each layer of metal interconnection layer includes metal interconnection lines And the interlayer dielectric layer, which requires etching the above-mentioned interlayer dielectric to form a connection hole (Via) and a trench (trench), and then deposit metal in the above-mentioned trench and connection hole, and the deposited metal forms a metal interconnection line. With the gradual improvement of the integration level of integrated circuits, the size of semiconductor devices continues to be scaled down. In B...

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Problems solved by technology

However, after strengthening the etching of the optical approximation layer in the through hole, due to the existence of etching inhomogeneity, the OPL in some through holes may be completely etched. If the OPL in the through hole 106 is completely etched At the same time, when the metal connection protection layer 103 at the bottom of the through hole 106 has defects, the copper in the metal connection layer 102 will also be etched as the OPL etching progresses, and the etched copper will gradually diffuse to the top of the trench and finally Formation of hillocks (hill-lock), thus causing bad

[0007] From the above analysis, it can be seen that if the through-hole etching is strengthened, the electromigration phenomenon of the device will be improved, but the occurrence probability of poor hill-lock will increase; if the through-hole etching is weakened, the poor hill-lock will be reduced, but the electrical migration of the device will increase. The phenomenon of migration defects will increase

Due to the non-uniformity of via etching, it is difficult to find suitable via etching conditions, resulting in poor hill-lock and device electromigration defects that cannot be improved at the same time

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