Semiconductor device and manufacturing method thereof

Abstract

Provided is a semiconductor device, comprising: multiple fins (1A, 1B), provided on a substrate (1) and extending along a first direction; multiple gate stack structures (9A, 9B), extending along a second direction and spanning each fin; multiple stress layers (7), provided in the fins at two sides of the gate stack structure and provided with multiple source and drain regions (7A) inside; and multiple channel regions (1C), provided between the multiple source and drain regions along the first direction, the multiple gate stacking structures surrounding the multiple channels. Also provided is a manufacturing method of the device. A hard mask and a dummy gate are combined to penetrate and corrode the fins located at the channel region, to self-aligningly form a metal-multigate-all-around nanowire, thereby enhancing the device performance.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a self-aligned multi-gate nanowire FET and a manufacturing method thereof. Background technique [0002] In the current sub-20nm technology, the three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control capability and suppresses leakage and short channel effects. [0003] For example, compared with traditional single-gate bulk Si or SOI MOSFETs, MOSFETs with double-gate SOI structures can suppress short-channel effects (SCE) and drain-induced barrier lowering (DIBL) effects, have lower junction capacitance, and can To achieve light channel doping, the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxide thickness (EOT). Compared with the double-gate device, ...

AI Technical Summary

Problems solved by technology

[0004] General nanowire three-dimensional multi-gate devices need to be integrated with the metal gate last gate process to maintain performance advantages, but the manufacturing process of these nanowire multi-gate devices is generally complicated and incompatible with mainstream processes, especially it is difficult to apply the current popular MG ( Gate of metal material) / HK (gate insulating layer of high-k material) gate stack structure

This limits the ability of 3D multi-gate devices to improve device performance

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