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IC chip stack package with high packaging density and good high-frequency performance and manufacturing method

A high-frequency performance, chip stacking technology, used in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve problems affecting high-frequency performance, restrict product packaging density, etc., to improve production efficiency and save production costs. Effect

Active Publication Date: 2017-01-04
TIANSHUI HUATIAN TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the current QFN and other packaging forms with a small number of pins and high-arc stacking cannot meet the requirements of multi-I / O low-arc bonding wires, which restricts product packaging density and affects the limitations of high-frequency performance.

Method used

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  • IC chip stack package with high packaging density and good high-frequency performance and manufacturing method
  • IC chip stack package with high packaging density and good high-frequency performance and manufacturing method
  • IC chip stack package with high packaging density and good high-frequency performance and manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0066] Wafers with bumps are thinned and diced using thick adhesive film to prevent chip bump scratches, chip warpage and double-knife scribing to prevent cracking. The thinning adopts rough grinding + fine grinding + corrosion + polishing, and The final thickness of the circle is 150μm, and the roughness of the back of the wafer is ≤0.4μm; when the wafer without bumps is thinned, the rough grinding + fine grinding + corrosion + polishing process is adopted, and the final thickness of the wafer is 100μm, and the surface roughness is ≤0.3μm . Paste a high-temperature UV film on the back of the thinned wafer with bumps and the back of the wafer without bumps, and then perform scribing, using an anti-fragmentation scribing process. Take a multi-turn QFN lead frame, use a high-temperature UV film with high-temperature baking and a device with a high-temperature UV film core, and place an IC chip without bumps on a multi-turn QFN lead frame at a temperature of 100°C Bake for 2 hou...

Embodiment 2

[0070] Wafers with bumps are thinned and diced using thick adhesive film to prevent chip bump scratches, chip warpage and double-knife scribing to prevent cracking. The thinning adopts rough grinding + fine grinding + corrosion + polishing, and The final thickness of the circle is 150 μm, and the roughness of the back surface of the wafer is ≤0.4 μm; when the wafer without bumps is thinned, the rough grinding + fine grinding + corrosion + polishing process is adopted, the final thickness of the wafer is 50 μm, and the surface roughness after thinning ≤0.3μm. Paste a high-temperature UV film on the back of the thinned wafer with bumps and the back of the wafer without bumps, and then perform scribing, using an anti-fragmentation scribing process. Use the flip-chip core loading machine to core the IC chip with bumps on the AAQFN lead frame, so that the bumps on the IC chip with bumps are bonded to the first inner pin on the AAQFN lead frame, and on the AAQFN lead frame The unde...

Embodiment 3

[0073]Wafers with bumps are thinned and diced using thick adhesive film to prevent chip bump scratches, chip warpage and double-knife scribing to prevent cracking. The thinning adopts rough grinding + fine grinding + corrosion + polishing, and The final thickness of the circle is 150μm, and the roughness of the back of the wafer is ≤0.4μm; when the wafer without bumps is thinned, the rough grinding + fine grinding + corrosion + polishing process is adopted, the final thickness of the wafer is 75μm, and the surface after thinning is rough Degree ≤ 0.3μm. Paste a high-temperature UV film on the back of the thinned wafer with bumps and the back of the wafer without bumps, and then perform scribing, using an anti-fragmentation scribing process. Use the flip-chip core loading machine to core the IC chip with bumps on the AAQFN lead frame, so that the bumps on the IC chip with bumps are bonded to the first inner pin on the AAQFN lead frame, and on the AAQFN lead frame The underfill...

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Abstract

An IC chip stacked package with high packaging density and good high-frequency performance and its manufacturing method. IC chips with even layers are stacked on a multi-turn QFN lead frame, the odd layers are IC chips without bumps, and the even layers are flip-chip IC chips. IC chips with bumps, IC chips without bumps are connected to the inner pins; IC chips with even layers are stacked on the AAQFN lead frame, the odd layers are IC chips with bumps, and the even layers are flip-chip IC chips without bumps , IC chips without bumps are connected to inner pins; adjacent IC chips are bonded by high-temperature UV film. Wafer thinning and dicing, chip loading, pressure welding, plastic packaging, pin separation, chemical plating, printing, product separation, inspection, testing, packaging, to produce IC chip stack packages with high packaging density and high frequency performance. The manufacturing method of the invention replaces the CPS produced by the substrate, realizes the flexible application of the IC chip to the CSP package of the lead frame, improves the production efficiency and saves the production cost.

Description

technical field [0001] The invention belongs to the technical field of electronic information automation components manufacturing, and relates to a multi-IC chip stack package, in particular to an IC chip stack package with high packaging density and good high-frequency performance, and the invention also relates to a package of the package Production method. Background technique [0002] With the expansion of the electronic market's demand for smaller, lighter and thinner multi-functional mobile phones and the growth of the application of PAD-level electronic devices, the electronic industry integrated circuit packaging has been developed in the direction of miniaturization and multi-function. It has become an important technical means to meet smaller, lighter and more functional products. It allows multiple IC chips to be stacked in a single package to double the capacity of a limited space; it directly interconnects the chips, making the bonding wire significantly shorte...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/495H01L21/50H01L21/60
CPCH01L2224/16145H01L2224/32245H01L2224/48091H01L2224/48247H01L2224/73265H01L2924/00014H01L2924/00
Inventor 慕蔚刘殿龙张易勒
Owner TIANSHUI HUATIAN TECH
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