Efficient secure chip power consumption attack test method

A power consumption attack and security chip technology, which is applied in the field of chip information security, can solve the problems of low accuracy of simulation attack methods, unsuitable for verifying security chip anti-power consumption analysis characteristics, and low reliability of results, etc.

Inactive Publication Date: 2014-03-26
JIANGSU SEUIC TECH CO LTD
View PDF6 Cites 12 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Some scholars use the simulation attack method designed by mathematical modeling. Although the attack is efficient and the cost is low, its accuracy is very low, the reliability of the result is not high, and it is not suitable for verifying the anti-power analysis characteristics of the security chip.
[0006]

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Efficient secure chip power consumption attack test method
  • Efficient secure chip power consumption attack test method
  • Efficient secure chip power consumption attack test method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0041] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0042] Such as figure 1 Shown is the overall framework of the security chip power consumption attack testing method of the present invention. There are three core parts in the security chip power consumption attack test method: a function simulation module, a power consumption simulation module and a power consumption analysis module. The basic process is to first synthesize the RTL code of the algorithm through the DC (Design Compiler, DC) tool to generate a circuit netlist file, and then load the test vectors necessary for the netlist such as plaintext and clock, and the standard cell library and timing parameters used by the netlist Simulate through VCS together to generate functional simulation waveforms. Functional simulation waveforms need to be converted into VCD files required for power simulation analysis. Then set the simulation en...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses an efficient secure chip power consumption attack test method. When a power consumption attack test is carried out on a secure chip in a design stage, the obtaining and processing method of a power consumption sample includes the steps of (1) obtaining the power consumption sample, (2) pre-processing the power consumption sample, (3) obtaining an assumed power consumption sample, and (4) calculating correlation coefficients and analyzing an attack result. According to the method, only power consumption points which change are sampled, large quantities of power consumption sample data are saved, the power consumption attack calculated amount is substantially reduced, and the method has the advantages of being high in evaluation efficiency and speed. More importantly, the power consumption attack test can be carried out in the design stage of the chip, the risk that the chip is designed again due to the fact that the safety performance of the chip produced in a stream line is not good is reduced and accordingly the design cycle of the secure chip is shortened.

Description

technical field [0001] The invention relates to the field of chip information security, in particular to an efficient power consumption attack testing method for a secure chip. Background technique [0002] Entering the 21st century, with the rapid development of science and technology, social informatization has become the general trend, life has become informatized, digitized and networked, and people's dependence on information is constantly increasing. With the development of computer, network, communication technology and integrated circuit technology, security chips are widely used in bank cards of automatic teller machines (Automatic Teller Machine, ATM), smart cards of access control systems in residential or corporate environments, and voice encryption chips in mobile phones. And other environments that require information security. Because the circuit structure inside the integrated circuit is very complex, and it has the characteristics of good sealing, not easy ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F21/55
CPCG06F21/57G06F30/30
Inventor 蔡志匡单伟伟刘君寅朱佳梁邵金梓黄丹丹
Owner JIANGSU SEUIC TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products