A kind of semiconductor device and its preparation method

Abstract

The invention relates to a semiconductor device and a preparation method thereof; the method comprises the steps of providing a semiconductor substrate having a support substrate, an oxide insulating layer and a semiconductor material layer laminated in sequence; forming a hard mask layer on the substrate; patterning the hard mask layer; forming a gap wall on a side wall of the hard mask layer; etching the semiconductor material layer so as to form a first grid electrode zone; oxidating a side wall of the semiconductor material layer so as to form a gate oxidation layer of the first grid electrode zone; depositing a second semiconductor material layer so as to form a first grid electrode; oxidating the top of the second semiconductor material layer; pattering the resting hard mask layer so at to form fin patterns; etching the semiconductor material layer so as to form a first fin, a second fin and a second grid electrode zone; forming a gate oxide layer on the second fin, and forming a gate oxidation layer of the second grid electrode zone on the first fin; depositing a third semiconductor material layer so as to form a second grid electrode. The method is easier to control.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular, the invention relates to a semiconductor device and a preparation method thereof. Background technique [0002] The improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, manufacturing and design challenges have led to the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs). Typical FinFETs are fabricated using thin vertical "fins" (or fin structures) extending from a substrate formed, eg, by etching away a portion of the silicon layer. A FinFET channel is formed in the vertical fin, a surrounding gate is formed above the fin, and the channel is controlled from both sides through the gate. Additionall...

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Problems solved by technology

[0006] At present, although the threshold voltage of the device can be controlled by the DG-FinFET device to eliminate or reduce the short channel effect, it is difficult to control the process when forming an asymmetric gate oxide, and the accuracy is poor, resulting in device yield and performance. Therefore, it is necessary to improve the above method to eliminate the above problems

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