Semiconductor device and manufacturing method thereof

Abstract

This invention discloses a semiconductor device, comprising a plurality of fins which are extended along a first direction on a substrate, a top gate which is extended along a second direction and goes across each fin, source-drain zones which are positioned on fins on two sides of the top gate, a channel region which is positioned between the source-drain zones, a gate bodies which are positioned among the plurality of the fins and under the top gate and extended long a second direction. According to the semiconductor device and the manufacture method thereof, the extra gate body is adopted to control the current leakage caused by the bottoms of the fins between the source zone and the drain zone, the junction capacity is reduced while the junction leakage current, and the reliability of the member is increased.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a FinFET with a body gate and a manufacturing method thereof. Background technique [0002] In the current sub-20nm technology, the three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control capability and suppresses leakage and short channel effects. [0003] For example, compared with traditional single-gate bulk Si or SOI MOSFETs, MOSFETs with double-gate SOI structures can suppress short-channel effects (SCE) and drain-induced barrier lowering (DIBL) effects, have lower junction capacitance, and can To achieve light channel doping, the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxide thickness (EOT). Compared with the double-gate device, the gate of t...

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Problems solved by technology

[0005] Among the above-mentioned structures and methods, although the FinFET on the SOI substrate has a simple structure and process, the cost of the substrate material is high, and it is not as easy to be used in mass production as the bulk Si substrate; the FinFET using PN junction isolation on the bulk silicon substrate utilizes Implantation junction isolation, the isolation effect is poor due to the restriction of implantation dose and depth, and the implantation process is difficult to control, and it is easy to introduce additional doping into the channel region to affect the conductivity of the device; the bulk silicon substrate is isolated by lateral selective oxidation The FinFET has complex process and high cost, high thermal oxidation temperature, and the channel region is easy to introduce additional stress and strain, which affects the conduction

In addition, these technologies are usually produced during the formation of silicon fins. When FinFETs are manufactured using the gate-last process, the isolation structure produced during the formation of silicon fins before the formation of dummy gates may be damaged in the subsequent process.

In addition, these current silicon fin trench isolation structures are usually formed along the vertical channel direction (hereinafter referred to as the XX' direction or the second direction, that is, the direction in which the gate lines extend). The isolation between the fins and the substrate in the channel direction (hereinafter referred to as the Y-Y' direction or the first direction, that is, the direction in which the fin lines extend) is not perfect

[0006] In summary, existing FinFET devices have difficulty controlling the leakage between the source and drain regions formed through the bottom of the fin

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