Method of semiconductor package realizing connection by bonding tab

Abstract

The invention discloses a semiconductor package for internal connection with connecting sheets, comprising: a plurality of chips, each of which has a plurality of top contact areas and bottom contact areas; a plurality of substrates for placing the The chip, the bottom contact area of ​​the chip is electrically connected to the substrate, and the substrate is provided with a plurality of external pins of the substrate; the connecting piece, the connecting piece is connected to a plurality of chips, and is used to connect a plurality of chips correspondingly arranged a plurality of top contact areas, thereby fixing the plurality of chips, and the ends of the connecting sheets are connected to the outside as the pins of the chips; a plastic package is used for packaging chips, substrates, and connecting sheets. The present invention In the process of manufacturing, multiple chips are fixedly connected through one or more connecting pieces, then packaged, and finally the connecting pieces are separated by cutting or grinding on the top of the package. Due to the fixed connection function of the connecting pieces, the present invention avoids the need for chips to be processed in the process. Misalignment during the process affects the circuit performance of the chip.

Description

technical field [0001] The invention relates to a semiconductor packaging structure and a manufacturing method, in particular to a semiconductor packaging and a manufacturing method thereof which are connected by connecting sheets. Background technique [0002] In order to meet the needs of miniaturization of electronic products, multi-chip semiconductor packaging has become a trend, and the semiconductor packaging of multi-chip modules carries multiple chips in a single package. [0003] For example, in the Chinese patent authorization announcement number CN201063342Y, a multi-chip packaging structure is disclosed, including: a first lead frame, including a first chip seat, a first inner pin and a second outer pin; a second lead frame, including a first Two chip seats and second inner pins; the second lead frame is located above or below the first lead frame, and the first lead frame is electrically connected to the second lead frame through the connector; the first chip is...

AI Technical Summary

Problems solved by technology

[0005] The above-mentioned prior art for chip packaging is to use wires for the connection between the chip and the lead frame, but in the packaging process of multiple chips connected by wires, the bonding and soldering reflow process usually make the chips prone to error. Movement, and due to the movement of the chip, a short circuit between the wires is caused at the same time, which affects the performance of the circuit. In addition, in the prior art, in order to increase the pins, cutting is performed at the bottom of the package, which has poor flexibility and increases the complexity of the process. , is not conducive to reducing production costs

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