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Energy-efficient pipeline circuit templates for high performance asynchronous circuits

An asynchronous circuit and asynchronous processing technology, applied in CAD circuit design, electrical digital data processing, special data processing applications, etc., can solve the problems of unstable equipment and difficult for synchronous designers to overcome.

Inactive Publication Date: 2014-06-18
CORNELL UNIVERSITY
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Problems solved by technology

In addition, process variations in the deep submicron range make devices less robust, and this issue makes it increasingly difficult for synchronous designers to overcome problems related to clock skew rate and clock distribution [Dally and Poulton1998]

Method used

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  • Energy-efficient pipeline circuit templates for high performance asynchronous circuits
  • Energy-efficient pipeline circuit templates for high performance asynchronous circuits
  • Energy-efficient pipeline circuit templates for high performance asynchronous circuits

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Embodiment Construction

[0037]Asynchronous quasi-delay-insensitive (QDI) circuits with robustness to process variations, no global clock dependencies, and inherently perfect clock gating represent a viable design alternative for future chip designs. QDI circuits have been used in a variety of high-performance, power-efficient asynchronous designs [Sheikh and Manohar 2010] [D. Fang and Manohar 2005], including fully realized and fabricated asynchronous microprocessors [Martin et al. 1997]. QDI circuits lose some energy efficiency gains when implementing handshaking between different parallel pipeline processes. In order to ensure the QDI behavior for each handshake, each upstream and downstream transition within the pipeline is checked, which results in a lot of handshaking circuitry and energy overhead. Each stage of the high-throughput QDI pipeline consists of only a small amount of logic. The large number of pipeline stages required for high throughput makes the handshaking overhead a large part o...

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Abstract

Asynchronous circuits and techniques are described for asynchronous processing without synchronization to a common clock. Two specific energy-efficient pipeline templates for high throughput asynchronous circuits are provided as examples based on single-track handshake protocol. Each pipeline contains multiple stages of logic. The handshake overhead is minimized by eliminating validity and neutrality detection logic gates for all input tokens as well as for all intermediate logic nodes. Both of these templates can pack significant amount of logic within each pipeline block, while still maintaining a fast cycle time.

Description

[0001] Priority and related applications [0002] Pursuant to 35 U.S.C. §119, this patent application claims priority to U.S. Provisional Application No. 61 / 514,589, filed August 3, 2011, entitled "Energy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits" right, and priority to U.S. Provisional Application No. 61 / 515,387, filed August 5, 2011, entitled "Energy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits." The entire disclosure contents of the above two applications are incorporated herein by reference as a part of this patent document. [0003] Federally Sponsored Research or Development [0004] This invention was made with government support under grants CNS-0834582 and CCF-042827 awarded by the National Science Foundation (NSF). The government has certain rights in this invention. Background technique [0005] Integrated circuits for signal processing can be configured as synchronous circuits and asynchronous circuits. T...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/00G06F9/38
CPCG06F9/3871G06F9/3869G06F30/35G06F1/12
Inventor R·马诺哈尔B·R·谢赫
Owner CORNELL UNIVERSITY
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