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Method of manufacturing semiconductor device

A semiconductor and device technology, applied in the field of manufacturing semiconductor devices, can solve problems such as reducing device reliability and achieve excellent characteristics

Active Publication Date: 2014-09-03
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] In Japanese Unexamined Patent Publication No. 2009-252841 (Patent Document 3), it is disclosed that diffusion of hydrogen into a gate insulating film of a transistor lowers reliability of the device

Method used

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  • Method of manufacturing semiconductor device
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  • Method of manufacturing semiconductor device

Examples

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no. 1 example

[0131] Referring now to the drawings, a description will be given of the structure of the semiconductor device in this embodiment.

[0132] -Structure Description-

[0133] figure 1 is a main sectional view showing the configuration of the semiconductor device in this embodiment. The semiconductor device in this embodiment has MISFETs (LT) and MISFETs (HT).

[0134] The MISFET (LT) is a MISFET formed in the core MIS formation region 1A, and has a gate length smaller than that of the MISFET (HT). The gate length of the MISFET (LT) is, for example, about 40 nm when its manufacturing process belongs to the 40-nm regular stage. Such a MISFET having a relatively small gate length is used, for example, in a circuit (also referred to as a core circuit or a peripheral circuit) for driving another element such as a memory MC. The driving voltage of the MISFET (LT) tends to be smaller than that of the MISFET (HT). The insulating film 3 of the MISFET (LT) may be thinner than that o...

no. 2 example

[0199] Referring now to the drawings, a description will be given below of the structure of the semiconductor device (semiconductor memory device) in this embodiment.

[0200] -Structure Description-

[0201] Figure 20 is a main sectional view showing the configuration of the semiconductor device in this embodiment. The semiconductor device in this embodiment has a MISFET (LT) and a memory cell (also referred to as a nonvolatile memory cell, a nonvolatile memory element, a nonvolatile semiconductor memory device, an EEPROM, or a flash memory).

[0202] The MISFET (LT) is a MISFET formed in the core MIS formation region 1A, and has a relatively small gate length. For example, the gate length of the MISFET (LT) is smaller than the sum of the gate length of the control gate electrode CG of the memory cell MC and the gate length of its memory gate electrode MG, and is, for example, about 40 nm. Such a MISFET having a relatively small gate length is used, for example, in a circ...

no. 3 example

[0291] Referring now to the drawings, a description will be given below of the structure of the semiconductor device (semiconductor memory device) in this embodiment.

[0292] -Structure Description-

[0293] Figure 44 is a main sectional view showing the configuration of the semiconductor device in this embodiment. The semiconductor device in this embodiment has MISFETs (LT), MISFETs (HT), and memory cells MC.

[0294] The MISFET (LT) is a MISFET formed in the core MIS formation region 1A, and has a gate length smaller than that of the MISFET (HT). The gate length of the MISFET (LT) is, for example, about 40 nm. Such a MISFET having a relatively small gate length is used, for example, in a circuit (also referred to as a core circuit or a peripheral circuit) for driving a memory MC. The driving voltage of the MISFET (LT) tends to be smaller than that of the MISFET (HT). The insulating film 3 of the MISFET (LT) may be thinner than that of the MISFET (HT).

[0295] On the...

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Abstract

To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Description

[0001] Cross References to Related Applications [0002] The disclosure of Japanese Patent Application No. 2013-040061 filed on February 28, 2013, including specification, drawings and abstract, is incorporated herein by reference in its entirety. technical field [0003] The present invention relates to a method of manufacturing a semiconductor device, which can be suitably used as a method of manufacturing a semiconductor device having, for example, MISFETs and nonvolatile memory cells. Background technique [0004] Examples of technologies that improve the characteristics of the MISFET include SMT (Stress Memory Technology). SMT is a technique of applying stress to a channel from above a gate electrode to strain crystals in the channel and improve carrier mobility in the channel. [0005] For example, in Japanese Unexamined Patent Publication No. 2010-205951 (Patent Document 1), there is disclosed a solid-stage image sensing device in which a first stress liner film (81)...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H01L21/318
CPCH01L29/66825H01L27/1157H01L27/1052H01L29/4234H01L21/3105H01L27/11573H01L21/8234H01L29/42324H01L29/66833H01L21/823468H01L21/823412H10B43/40H10B43/35H01L29/40117H01L27/0922H01L21/823418H01L21/28518H01L29/7847
Inventor 鳥羽功一茶木原启川嶋祥之齐藤健太郎桥本孝司
Owner RENESAS ELECTRONICS CORP
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