A method for preparing a high withstand voltage super junction terminal structure
A junction termination and withstand voltage technology, which is applied in the field of preparation of high withstand voltage superjunction termination structures, can solve problems such as low withstand voltage, avalanche breakdown, and reduce device reliability, and achieves improved breakdown voltage, improved reliability, and improved reliability. The effect of high current handling capability
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Embodiment 1
[0030] This example includes the following steps:
[0031] Step 1: Epitaxial N- epitaxial layer 2 on N+ substrate 1, such as figure 2 shown;
[0032] Step 2: Using photolithography and bulk silicon etching process, a plurality of first grooves 8 with a depth of h are formed on the upper layer of the N-epitaxial layer 2 in the part of the termination region II, as shown in image 3 shown;
[0033] Step 3: Using photolithography and bulk silicon etching processes, perform second groove etching in the cell region I and terminal region II at the same time, and generate a plurality of first grooves in the upper layer of the N-epitaxial layer 2 in the cell region and terminal region respectively. The second groove, the second groove in the terminal area should correspond to the first groove 8 one by one, and the formed structure is as follows Figure 4 As shown, the second groove 3 in the terminal area will be deeper than the second groove 4 in the cell area, and the total depth...
Embodiment 2
[0044] Such as Figure 13 As shown, the difference between this example and the first example lies in that the semiconductor pillars 83 of the second conductivity type in the termination region II are connected. The preparation method of this example only needs to change the pattern of the mask plate for bulk silicon etching in step 2, and the rest of the steps are the same as in the first embodiment.
Embodiment 3
[0046] Such as Figure 14 As shown, the difference between this example and the first example lies in that the semiconductor pillars 83 of the second conductivity type in the terminal region II are partially connected. The preparation method of this example only needs to change the pattern of the mask plate for bulk silicon etching in step 2, and the rest of the steps are the same as in the first embodiment.
[0047] The invention is also applicable to the preparation of P-channel super-junction VDMOS devices, super-junction DIODE or super-junction IGBT.
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