[0021] The closed-loop control FPGA experimental platform structure of the epilepsy neural cluster network of the present invention will be described below in conjunction with the accompanying drawings.
[0022] The design idea of the closed-loop control FPGA experimental platform of the epilepsy neural cluster network of the present invention is to first set up an epilepsy neural cluster network model with multiple neural clusters and complex coupling on the FPGA; then design PI type iterations independently of the neural cluster network model on the FPGA Learning controller, PI type iterative learning control signal is applied to the model as an external current stimulus, and the pathological discharge mode of the epileptic neural cluster network is changed through stimulation to make it produce normal discharge; finally, the software interface of the host computer is designed, and the software interface of the host computer is set by setting parameters And transmit it to the FPGA chip to realize the configuration of network coupling structure, excitatory synapse gain, controller parameters and initial state. Different network coupling structure parameters and excitatory synapse gain can simulate the discharge characteristics of normal state and epileptic state. At the same time, the dynamic discharge data of the neural cluster network in the FPGA chip can also be uploaded to the host computer, and the discharge dynamic waveform can be displayed on the software interface of the host computer. The experimental platform is composed of interconnected FPGA chip and host computer. Among them, the FPGA chip is used to realize the epilepsy neural cluster network model and the PI type iterative learning controller, and the upper computer is used to design the upper computer software interface and communicate with the FPGA.
[0023] The epilepsy neural cluster network model is composed of mutually coupled neural cluster models. The basic idea of the epileptic neural cluster model is to make excitatory and inhibitory cell groups interact to generate neural shocks. For a single epileptic neural cluster model, the Euler method is used to discretize the model in the FPGA, and it is constructed using pipeline technology, so that the complex constant Parallel computation of differential equations. The idea of pipelining is actually to use the delay register to divide the mathematical model into several sub-operation processes. In each clock cycle, each sub-operation process can perform operations on different neural clusters and at different times at the same time, and the model data is cross-saved in the SRAM register. , and passed with the clock. In models of neural clusters in epilepsy, excitatory and inhibitory cell populations interact to generate neural oscillations. A cerebral cortical region can be regarded as composed of three different neural populations: excitatory astrocytes, excitatory pyramidal cells, and inhibitory interneurons. The network coupling structure can be represented by a coupling strength matrix. The coupling strength matrix of the network and the excitatory synaptic gain matrix of the neural group are input by the host computer operation interface, stored in the peripheral register SRAM, and called synchronously during calculation, so that independent The parameter adjustment of the neural cluster and the change of the network structure of the neural cluster network finally realize the network model. Different model parameters will produce different discharge patterns, so different parameters can be set from the operation interface to make the model generate normal and epileptic discharge patterns respectively.
[0024] Based on the neural cluster model of epileptic state closed-loop control FPGA experimental platform, the neural cluster is set to be abnormally excited, and all parameters except the excitatory synaptic gain are taken as standard values, and the epilepsy operation platform is run to gradually increase each neural cluster Because the control energy acting on the abnormally excited neural cluster is larger than the control energy acting on the other two neural clusters that originally exhibited normal activities, the abnormally excited neural cluster in the network is determined. Because the purpose of direct proportional integral control at this time is only to determine the abnormally excited nerve clusters, not to control epileptic spikes, so its value is very small and the running time is very short, and the energy acting on each nerve cluster is very small to ensure the safety of the human body. Harmless, after the abnormally excited nerve cluster is determined, the control strategy is used to control the nerve cluster to control the epileptic spike, and the complete diagnosis and control experiment process can be completed.
[0025] The PI type iterative learning controller: iterative learning control is different from most existing control methods, it uses the past control information to construct the current control effect to the greatest extent possible, the past control information includes the past tracking error signal and control input signal. Iterative learning control is realized by learning-based memory. First, the memory is used to store past control information, and then the stored control information is combined in a certain way to form the feed-forward part of the current control action. At the same time, the feedback part of the current control information can be combined. Together form the current control role. The PI type iterative learning control signal is connected to the input of the controlled neural cluster model as a stimulus input. Applying the control signal in different neural clusters will improve epilepsy symptoms, so it is necessary to design a data selector to realize the control signal in different neural clusters. switch between to achieve control of different symptoms. Different control signals have different control effects. Therefore, the proportional parameters and integral parameters of the control signals can be adjusted on the software interface of the host computer, and the PI type iterative learning controller can be configured through USB transmission to the FPGA, and the control parameters can be quickly and quantitatively optimized. While controlling the disease, the power consumption is minimized to achieve the goal of optimal control.
[0026] Described upper computer software interface: the writing of upper computer software interface adopts VB (Visual Basic) software development and realizes, and the development process is convenient and intuitive, is the high-level programming language of visualization, object-oriented, driven by the event, what finally presents in front of the user is The operation interface similar to the real experimental instrument can realize real-time data acquisition, waveform display and data analysis and processing.
[0027] The PI type iterative learning control FPGA experimental platform of the epilepsy neural cluster network of the present invention is composed of an interconnected FPGA chip 1 and a host computer 2 . Among them, the FPGA chip 1 is used to realize the epileptic state closed-loop control neural cluster network model 3 and the PI type iterative learning controller 4 , and the host computer 2 is used to design the host computer software interface 5 and communicate with the FPGA chip 1 through the USB interface 6 . To illustrate:
[0028] Neural cluster network model for closed-loop control of epileptic states 3
[0029] like figure 1 As shown, the hardware experiment platform is designed, using Altera’s low-power consumption CycloneⅣEP4CE115F29C7N FPGA chip 1, using a digital signal processing development tool DSP Builder launched by Altera for graphical programming and then converting it into VHDL language. According to the mathematical model of the neural cluster, The pipeline data model 9 of the normal neural cluster network and the pipeline data path model 10 of the epilepsy neural cluster network are discretized and constructed by using the Euler method. Each pipeline data path model of the neural cluster network is composed of mutually coupled epilepsy neural cluster models 37 . The data input bus 7 receives the data set by the host computer software interface 5 to the FPGA epileptic state closed-loop control system, and the key data such as the nerve cluster membrane potential signal 17 and the PI type iterative learning control signal 25 are uploaded to the host computer through the data output bus 8 Real-time display and analysis of the dynamic characteristics of the epileptic state neural cluster network. like figure 2 As shown, the epileptic neural cluster model 37 is mainly composed of addition, multiplication, lookup table, and shift register operation modules, which are mutually coupled excitatory pyramidal cell neuron pipeline data pathway 42, excitatory astrocyte neuron pipeline data pathway 43, Inhibitory interneuron I pipeline data path 44, inhibitory interneuron II pipeline data path 45, receive noise signal 39 generated by random Gaussian distribution generator 46, through the interaction between pyramidal cells and interneuron cluster C1 constant 47 , C2 constant 48 to configure the characteristics of the neural cluster, and design the depth of the pipeline according to the network scale of the neural cluster. All data paths run synchronously under the unified clock, and according to the structure of FPGA, the conversion of hardware description language is realized through QUARTUSⅡ software. Among them, S(y) is a nonlinear Sigmoid function. A single neural group in a model coupled with multiple neural clusters can be represented by eight ordinary differential equations. Each of the two channels is a module, which outputs simulated EEG signals, and finally obtains the membrane potential of the neural cluster. Signal 17.
[0030] After the neural cluster model is built, the coupling relationship between them is established to construct the neural cluster network model. like image 3 As shown, changing the coupling strength signal 26 and the excitatory synapse gain signal 27 through the host computer software interface 5 can change the structure of the network, thereby obtaining two types of networks, normal neural clusters and pathological neural clusters. Normal neural cluster pipeline data model 9, epileptic neural cluster pipeline data model 10 receive initial value signal 24 stored in initial value module 19, PI type iterative learning control signal 25 generated by PI type iterative learning controller 4, excitatory synapse gain matrix 21 The stored excitatory synapse gain signal 27 is processed, and the models 9 and 10 simultaneously receive the noise signal 39 generated by the noise generation module 18 realized by the look-up table technology, and pass through the pipeline data model 9 of the normal neural cluster network and the neural cluster network of epilepsy The neural cluster membrane potential signal 17 generated by the operation of the pipeline data model 10 is input to the PI type iterative learning algorithm controller 4 to complete the control based on the iterative learning algorithm. The coupling strength matrix 20 and the excitatory synapse gain matrix 21 are stored in the memory module. In addition to calling the above two, the epileptic neural cluster network pipeline data model 10 needs to call the PI output by the PI type iterative learning controller 4 during calculation. Type iterative learning control signal 25. When calculating the coupling between networks, the method is to multiply the synaptic current signal 38 generated in the epilepsy neural cluster model 37 by the coupling strength matrix 20 as the input value of the network coupling, so that the coupling relationship of the neural cluster network can be realized, and finally the epilepsy Neural Cluster Network Model 2.
[0031] The memory module 30 accepts the corresponding parameters input by the host computer software interface 5 for storage, and realizes synchronous calling during the calculation process of the pipeline, which includes the proportional parameter matrix 22, the integral parameter matrix 23, the coupling strength matrix 20 and the excitatory synapse gain matrix 21. It is completed by FPGA-based off-chip storage technology memory SRAM.
[0032] PI Type Iterative Learning Controller 4
[0033] The PI type iterative learning controller 4 uses the pipeline model to design a signal generator in the FPGA chip 1 for simulation. It includes three identical controllers, which are respectively composed of digital PI controller I11, iterative learning module I14, and digital PI controller II12. and iterative learning module Ⅱ15, digital PI controller Ⅲ13 and iterative learning module Ⅲ16, such as Figure 4shown. Taking one group as an example, it receives the membrane potential data 40 of the normal nerve cluster and the membrane potential data 41 of the epileptic nerve cluster for pipeline calculation, generates a PI type iterative learning control signal 25, and applies it to the pipeline data model 10 of the epileptic nerve cluster as an external current, Then design a data selector 36 to switch between different neural clusters, observe the size of the control signal and the different effects when it acts on different positions, so as to realize the control of epilepsy symptoms; at the same time, the PI type iterative learning controller 4 can The proportional parameter signal 28 and the integral parameter signal 29 transmitted by the host computer software interface 5 are received to optimize the PI type iterative learning controller 4 to achieve the control effect while minimizing the energy consumption of the control signal.
[0034] PC software interface 5
[0035] like Figure 5 As shown, in the host computer 2, the VB language programming method is used to design the host computer software interface 5. The FPGA chip 1 realizes data communication with the host computer software interface 5 through the USB device, and the host computer software interface 5 receives data from the FPGA chip 1 through the USB device. , the data obtained by the epileptic state closed-loop control neural cluster network model 3 calculation and the PI type iterative learning controller 4 transmitted by the USB interface 6; Closed-loop control neural cluster network model 3 and PI type iterative learning controller 4 for parameter configuration. VB is a visual, event-driven, object-oriented high-level programming language. It adopts a GUI system that can easily create application programs, and at the same time can develop complex programs. It can take into account data processing and storage, and ensures continuous data implementation. collection function. The upper computer software interface 5 design is divided into five parts: the upper computer software operation interface button part 31 realizes the control for the basic operation of the upper computer, including control application, start/stop state switching, refresh data, analysis data, help menu and display Waveform; the upper computer software operation interface controller configuration part 32 can modify the key parameters of the controller; the upper computer software operation interface neural group parameter configuration part 33 can realize the configuration of the neural cluster initial value parameter, network structure, and synaptic gain parameters; The computer software operation interface waveform display part 34 can realize the release point waveform of different neural groups in the neural group network and the corresponding control signal waveform; the upper computer software operation interface signal characteristic display part 35 can realize the energy and amplitude of the corresponding control signal, It is convenient to quantitatively judge the pros and cons of the control.
[0036] FPGA experiment platform
[0037] The neural cluster network model of closed-loop control epileptic state closed-loop control based on module discrete, fixed-step, and fixed-point arithmetic is written by DSP Builder, and then converted into a hardware description language. Compile the complete operation logic and program structure through QUARTUSⅡ software; compile, analyze and synthesize, layout and route, and download it to the FPGA chip 1 for operation. The normal nerve cluster membrane potential data 40, the epileptic nerve cluster membrane potential data 41 and the PI type iterative learning control signal 25 generated by the operation of the FPGA chip 1 are uploaded via USB. Conduct analytical research.
