Substrate chip carrier CSP package and production method thereof

Abstract

The invention provides a substrate chip carrier CSP package and a production method thereof. The package comprises a substrate having a middle supporting layer, opposite side walls of the middle supporting layer are provided with a plurality of connecting holes, a first metal layer is formed in each connecting hole, two end faces of the middle supporting layer are provided with first bonding pads and second bonding pads having the same quantity with the connecting holes, two ends of each first metal layer are respectively connected to the corresponding first bonding pad and the corresponding second pad, the pipe core adhering area of the middle supporting layer is provided with a plurality of ventilation holes in which cylindrical second metal layers are formed, the bonding pads of an IC chip are connected to the second bonding pads, a package body is fixedly packaged on the substrate. The substrate chip carrier CSP package is produced through the steps of thinning and scribing a wafer, connecting pipe cores by adhesive, bonding by a wire, packaging, marking, cutting and separating, testing and visually inspecting. The package body is compact in size, applied to IC components with fewer leading-out terminals, and replaces TSSOP and other conventional packaging; for an IC chip which is 0.350mm thick, the packaging thickness can be lower than 1mm.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging for electronic device manufacturing, and relates to a CSP package, in particular to a substrate chip carrier CSP package; the invention also relates to a manufacturing method of the package. Background technique [0002] With the development of the shape of electronic chip packages, the method of mounting integrated circuits has changed from the insertion type to the surface mount type (STM). STM has realized the high density, thinning and light weight of IC packaging. Tape automated bonding (TAB) method, flip chip method. In recent years, due to the rapid development of wireless communication devices such as smartphones, integrated circuit packaging has increasingly high requirements for the shape of the package. Conventional lead frame miniaturized plastic packages, such as TSSOP and TQFP, must achieve a package thickness of less than 1mm. Package, the die must be thinned to 0.2...

AI Technical Summary

Problems solved by technology

In recent years, due to the rapid development of wireless communication devices such as smartphones, integrated circuit packaging has increasingly high requirements for the shape of the package. Conventional lead frame miniaturized plastic packages, such as TSSOP and TQFP, must achieve a package thickness of less than 1mm. Package, the die must be thinned to 0.254mm, and at the same time, due to the large distribution area of ​​the lead frame pins, the lead frame carrier area is small, it is difficult to accommodate a larger die, and the distribution area of ​​the pins accounts for a large part of the package installation. The proportion of the area is also larger

In addition, with the increasing number of transistors in the chip, the heat generation is also increasing. In the case that the chip area does not increase significantly, the heat generation density of the device is getting higher and higher, and the problem of overheating has become a current constraint on electronic device technology. development bottleneck

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