Substrate chip carrier CSP package and production method thereof

A technology of substrate sheet type and manufacturing method, which is applied in the field of electronic device manufacturing and semiconductor packaging, and can solve problems such as large specific gravity, difficulty in accommodating dies, and high heat generation density of devices

Inactive Publication Date: 2014-10-29
TIANSHUI HUATIAN TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In recent years, due to the rapid development of wireless communication devices such as smartphones, integrated circuit packaging has increasingly high requirements for the shape of the package. Conventional lead frame miniaturized plastic packages, such as TSSOP and TQFP, must achieve a package thickness of less than 1mm. Package, the die must be thinned to 0.254mm, and at the same time, due to the large distribution area of ​​the lead frame pins, the lead frame carrier area is small, it is difficult to accommodate a larger die, and the distribution area of ​​the pins accounts for a large part of the package installation. The proportion of the area is also larger
In addition, with the increasing number of transistors in the chip, the heat generation is also increasing. In the case that the chip area does not increase significantly, the heat generation density of the device is getting higher and higher, and the problem of overheating has become a current constraint on electronic device technology. development bottleneck

Method used

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  • Substrate chip carrier CSP package and production method thereof
  • Substrate chip carrier CSP package and production method thereof
  • Substrate chip carrier CSP package and production method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0045] The surface of the wafer is thinned by the thinning process of coarse grinding + fine grinding + polishing; the thickness of the wafer after rough grinding is 350 μm, and the thickness of the wafer after fine grinding is 280 μm; polishing makes the surface roughness of the wafer reach 0.05 μm ~ 0.12 μm; the back of the thinned wafer is pasted with a blue film, baked, and then the wafer is cut into individual IC chips by a double-knife scribing process; when scribing, the depth of the first knife mark is the thickness of the thinned wafer 2 / 3 of the thickness; the second knife directly separates the wafer into individual IC chips, and leaves obvious knife marks on the blue film pasted on the back of the wafer, which cannot penetrate the blue film; send the substrate to On the loading table of the chip loader, the diced wafer is placed on the wafer workbench, and the glue writing system equipped with the core loader is used to draw glue on the die bonding area on the subst...

Embodiment 2

[0047] The surface of the wafer is thinned by the thinning process of coarse grinding + fine grinding + polishing; the thickness of the wafer after rough grinding is 360 μm, and the thickness of the wafer after fine grinding is 290 μm; the polishing process makes the surface roughness of the wafer reach 0.05-0.12 μm; paste the blue film on the back of the thinned wafer, bake, and cut the wafer into individual IC chips by double-knife scribing process; when scribing, the depth of the first knife mark is the thinned wafer 2 / 3 of the thickness, the second knife directly separates the wafer into individual IC chips, and leaves obvious knife marks on the blue film pasted on the back of the wafer, and the blue film cannot be scratched through; send the substrate to the The loading table of the core machine, the diced wafer is placed on the wafer workbench, and the glue writing system equipped with the core loader is used to draw glue on the die bonding area on the substrate, and the ...

Embodiment 3

[0049]The thinning process of rough grinding + fine grinding + polishing is used to thin the wafer surface. The thickness of the wafer after rough grinding is 340 μm, and the thickness of the wafer after fine grinding is 270 μm; polishing makes the surface roughness of the wafer reach 0.05 μm ~ 0.12 μm; paste the blue film on the back of the thinned wafer, bake, and cut the wafer into individual IC chips by double-knife scribing process; when scribing, the depth of the first knife mark is the thinned wafer 2 / 3 of the thickness, the second knife directly separates the wafer into individual IC chips, and leaves obvious knife marks on the blue film pasted on the back of the wafer, and the blue film cannot be scratched through; send the substrate to the On the loading table of the core machine, place the diced wafer on the wafer workbench, use the adhesive writing system equipped with the core loader to draw glue on the die bonding area on the substrate, and use the thimble to lift...

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Abstract

The invention provides a substrate chip carrier CSP package and a production method thereof. The package comprises a substrate having a middle supporting layer, opposite side walls of the middle supporting layer are provided with a plurality of connecting holes, a first metal layer is formed in each connecting hole, two end faces of the middle supporting layer are provided with first bonding pads and second bonding pads having the same quantity with the connecting holes, two ends of each first metal layer are respectively connected to the corresponding first bonding pad and the corresponding second pad, the pipe core adhering area of the middle supporting layer is provided with a plurality of ventilation holes in which cylindrical second metal layers are formed, the bonding pads of an IC chip are connected to the second bonding pads, a package body is fixedly packaged on the substrate. The substrate chip carrier CSP package is produced through the steps of thinning and scribing a wafer, connecting pipe cores by adhesive, bonding by a wire, packaging, marking, cutting and separating, testing and visually inspecting. The package body is compact in size, applied to IC components with fewer leading-out terminals, and replaces TSSOP and other conventional packaging; for an IC chip which is 0.350mm thick, the packaging thickness can be lower than 1mm.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging for electronic device manufacturing, and relates to a CSP package, in particular to a substrate chip carrier CSP package; the invention also relates to a manufacturing method of the package. Background technique [0002] With the development of the shape of electronic chip packages, the method of mounting integrated circuits has changed from the insertion type to the surface mount type (STM). STM has realized the high density, thinning and light weight of IC packaging. Tape automated bonding (TAB) method, flip chip method. In recent years, due to the rapid development of wireless communication devices such as smartphones, integrated circuit packaging has increasingly high requirements for the shape of the package. Conventional lead frame miniaturized plastic packages, such as TSSOP and TQFP, must achieve a package thickness of less than 1mm. Package, the die must be thinned to 0.2...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/367H01L21/56
CPCH01L24/73H01L2224/32225H01L2224/48227H01L2224/73265H01L2924/15162H01L2924/1531H01L2924/1815H01L2924/00012
Inventor 邵荣昌慕蔚李习周王永忠张易勒胡魁杨文杰
Owner TIANSHUI HUATIAN TECH
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