Method for preparing a plasma nitrided gate dielectric layer

A gate dielectric layer, plasma nitridation technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem that the equivalent thickness of oxide cannot be reduced, gate leakage cannot be effectively reduced, and device reliability cannot be reduced. problems, to achieve the effect of reducing leakage current density, increasing nitrogen content, and improving reliability

Active Publication Date: 2014-12-10
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
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Problems solved by technology

In this method, the nitrogen content is still not high enough to reduce the equivalent thickness of the oxide, effectively reduce the gate leakage and increase the driving current, which affects the reliability of the device.

Method used

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  • Method for preparing a plasma nitrided gate dielectric layer
  • Method for preparing a plasma nitrided gate dielectric layer
  • Method for preparing a plasma nitrided gate dielectric layer

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Embodiment Construction

[0031] The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0032] The invention provides a method for preparing a plasma nitride gate dielectric layer, such as figure 1 As shown, it is a schematic flow chart of a method for preparing a plasma nitrided gate dielectric layer according to an embodiment of the present invention, Figure 2 ~ Figure 4 It is a schematic diagram of the structure formed by preparing the plasma nitrided gate dielectric layer according to the above process in the embodiment of the present invention.

[0033] Specifically include the following ste...

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Abstract

The invention provides a method for preparing a plasma nitrided gate dielectric layer. The method is characterized in that the method includes the steps of providing a substrate, forming a silicon dioxide layer on the substrate and doping nitrogen into a silicon oxide layer under the temperature condition of minus 100 degrees to 0 degree. With the nitrogen doped under the low temperature of minus 100 degrees to 0 degree; diffusion effect of nitrogen ions is reduced; more nitrogen ions gather on the upper surface of the silicon dioxide layer; more bonding between Si-O bond and nitrogen ions is interrupted; nitrogen content on the upper surface of the plasma nitrided gate dielectric layer is increased. Thus, not only is leakage current density reduced but also a high gate capacitance is provided. Furthermore, reliability of the device is improved, and B+ is inhibited from diffusing from gate polysilicon to gate oxide.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a plasma nitride gate dielectric layer. Background technique [0002] Integrated circuits are made up of millions of basic building blocks such as transistors, capacitors and resistors. A transistor usually includes a source (Source), a drain (Drain) and a gate stack, and the composition of the gate stack is to form a dielectric layer (usually silicon dioxide) above the substrate (silicon), and then The dielectric layer is covered with a thin film (such as polysilicon) as an electrode. [0003] With the rapid development of Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI), the size of MOS devices has been continuously reduced. In order to increase the response speed of the device, increase the driving current and the capacity of the storage capacitor, the thickness of the silicon dioxide gate dielectric layer in the d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336
CPCH01L21/28158H01L21/28255
Inventor 肖天金邱裕明温振平
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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