Unlock instant, AI-driven research and patent intelligence for your innovation.

PMOS transistor, forming method of PMOS transistor, semiconductor device and forming method of semiconductor device

A technology of transistors and semiconductors, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as increased compressive stress, achieve the effects of increasing compressive stress, improving crystal quality, and improving performance

Active Publication Date: 2014-12-24
SEMICON MFG INT (SHANGHAI) CORP
View PDF3 Cites 8 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, when testing the PMOS transistor including the buffer stress layer, it is found that the compressive stress in the channel region of the PMOS transistor does not increase significantly, and the performance of the PMOS transistor can be improved by adding a buffer stress layer between the semiconductor substrate and the silicon germanium layer. limited effect

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • PMOS transistor, forming method of PMOS transistor, semiconductor device and forming method of semiconductor device
  • PMOS transistor, forming method of PMOS transistor, semiconductor device and forming method of semiconductor device
  • PMOS transistor, forming method of PMOS transistor, semiconductor device and forming method of semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0055] refer to figure 1 A semiconductor substrate 201a is provided, in which shallow trench isolation structures 203 are formed, and the semiconductor substrate 201a between adjacent shallow trench isolation structures 203 is an active region of the formed PMOS transistor.

[0056] In this embodiment, the material of the semiconductor substrate 201a is single crystal silicon or silicon on insulator. The material of the shallow trench isolation structure 203 is silicon oxide, and the formation process of the shallow trench isolation structure 203 is well known to those skilled in the art, and will not be repeated here.

[0057] continue to refer figure 1 , forming a first gate structure 205 on the semiconductor substrate 201a.

[0058] Specifically, the first gate structure 205 includes a first gate dielectric layer 205a on the semiconductor substrate 201a and a first gate electrode 205b on the first gate dielectric layer 205a.

[0059] The material of the first gate diel...

no. 2 example

[0133] refer to Figure 12 ,exist image 3 After the semiconductor structure is formed, the image 3 The buffer stress material layer 215a is dry etched. The buffer stress layer 215c formed after dry etching is as follows Figure 12 shown.

[0134]Specifically, the temperature range of the dry etching is 0°C-1000°C, the pressure range is 0torr-2000torr, the power range of the RF power supply is 0W-1000W, the range of the RF bias voltage is 30V-2000V, and the etching gas is One or any combination of HCl, HBr and HF, the flow rate of the etching gas ranges from 0 sccm to 500 sccm. At this time, dry etching is image 3 The etch rate of the buffer stress material layer 215a on the bottom of the first groove 213b is greater than the etch rate of the buffer stress material layer 215a on the sidewall of the first groove 213b, so that image 3 The thickness of the stress buffering material layer 215a on the bottom of the first groove 213b gradually approaches the thickness of th...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a PMOS transistor, a forming method of the PMOS transistor, a semiconductor device and a forming method of the semiconductor device. The forming method of the PMOS transistor comprises the steps that a semiconductor substrate is provided; a first grid electrode structure is formed on the semiconductor substrate; first grooves are formed in the positions, on the two sides of the first grid electrode structure, of the semiconductor substrate; stress buffering material layers are formed on the bottoms and the side walls of the first grooves and are etched to form stress buffering layers, and the ratio of the thickness of the stress buffering layers at the bottoms of the first grooves to the thickness of the stress buffering layers on the side walls of the first grooves is 1:1 to 0.8; main stress layers are formed in the first grooves with the stress buffering layers. The performance of the PMOS transistor formed by the method and the performance of the semiconductor device formed by the method are good.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a PMOS transistor and its forming method, a semiconductor device and its forming method. Background technique [0002] Metal-oxide-semiconductor (MOS) transistors have become common semiconductor devices in integrated circuits. The MOS transistors include: P-type metal oxide semiconductor (PMOS) transistors and N-type metal oxide semiconductor (NMOS) transistors. [0003] As element density and integration of semiconductor devices increase, the gate size of PMOS transistors or NMOS transistors becomes shorter than before. However, the shortening of the gate size of the PMOS transistor or the NMOS transistor will produce a short channel effect, thereby generating a leakage current and affecting the electrical performance of the CMOS transistor. In the prior art, the carrier mobility is mainly increased by increasing the stress of the channel region of the tra...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/336H01L29/78H01L29/06
CPCH01L29/66636H01L29/7848
Inventor 韦庆松于书坤
Owner SEMICON MFG INT (SHANGHAI) CORP