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A kind of knotless nanowire finfet and its manufacturing method

A production method and nanowire technology, applied in nanotechnology, nanotechnology, nanotechnology for information processing, etc., to achieve the effects of reducing process costs, improving performance, and simplifying the production process

Active Publication Date: 2021-06-04
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the manufacturing cost of the all-around gate junctionless field effect transistor is much higher than that of the traditional gate fin field effect transistor

Method used

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  • A kind of knotless nanowire finfet and its manufacturing method
  • A kind of knotless nanowire finfet and its manufacturing method
  • A kind of knotless nanowire finfet and its manufacturing method

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Embodiment Construction

[0034] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0035] For a thorough understanding of the present invention, a detailed description will be provided in the following description to illustrate the method of the present invention for improving particle defects during film deposition. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

[0036] It should be noted ...

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Abstract

The invention relates to a junctionless nanowire FinFET semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor substrate; forming an epitaxial layer on the semiconductor substrate; patterning the epitaxial layer and part of the semiconductor a substrate to form a fin structure and a nanowire structure on the fin structure; a gate structure is formed on the fin structure and the nanowire structure. The junctionless nanowire FinFET semiconductor device formed according to the present invention has a relatively large current when the device is in the open state, and a small current when the device is in the off state, and the performance of the FinFET is greatly improved relative to that of the FinFET. Because the planar device also has a larger on-off ratio, the whole process is fully compatible with the existing process, and the fabrication method of the transistor is suitable for small-sized semiconductor substrates, and its fabrication cost is lower than that of a nanowire cylinder surrounded by a gateless transistor. The manufacturing cost of the junction field effect transistor is lower, so the manufacturing process of the transistor is simpler, and the process cost is reduced at the same time.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a semiconductor device combining a fin field effect transistor (FinFET) and a junctionless nanowire field effect transistor and a manufacturing method thereof. Background technique [0002] Integrated circuits (ICs) have grown from a handful of interconnected devices fabricated on a single silicon chip to millions of devices. Current ICs offer performance and complexity far beyond what was originally imagined. To achieve improvements in complexity and circuit density (i.e., the number of devices that can be packed into a given chip area), the size of the smallest device feature, also known as device "geometry," has become smaller with each IC generation. Small. Semiconductor devices are now fabricated with features that span less than a quarter of a micron. [0003] With the continuous development of semiconductor technology, the improvement of integrated circuit perfor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/335H01L21/336H01L29/775H01L29/786B82Y10/00
CPCH01L29/0669H01L29/66795H01L29/785H01L29/7853H01L29/7854
Inventor 黄新运
Owner SEMICON MFG INT (SHANGHAI) CORP
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