Method for manufacturing an embedded package and structure thereof

Abstract

A method for manufacturing an embedded package comprises the steps of: coupling at least one first embedded body including at least one connection port with a first circuit substrate and packaging the first embedded body and the first circuit substrate to form a package; and exposing the connection port of the package on an outer side of the package for other electronic carriers to couple with. The invention can overcome the disadvantage of the conventional System in Package manufacturing process which integrally packages multiple ICs in a same package to result in discard of the entire package because of failure of a single IC. The method of the invention makes assembly simpler, expansion, test and replacement of IC components easier, and also can reduce manufacturing time and accumulated heat, lower the cost and improve yield rate.

Description

technical field [0001] The invention relates to a packaging body technology and its structure, in particular to an integrated packaging body technology with an embedded seat body and its structure. Background technique [0002] In recent years, semiconductor packaging technology includes two-dimensional System on Chip (SoC), which aims to integrate electronic systems into a single chip integrated circuit, and has the advantages of low power consumption, high performance, and small mounting area. , but the design time of the system single chip is too long, and different components are packaged on the same IC, the IC produced by it still occupies a considerable area, and its application range is limited. [0003] System-in-Package (SiP) is a new type of packaging technology, which can configure all or most of the electronic functions of a system or subsystem on an integrated substrate. Compared with SOC, it has more miniaturization, high function, and development The advantag...

AI Technical Summary

Problems solved by technology

[0004] However, the technical threshold and manufacturing cost of TSV 3D IC technology are still too high, and the application is not yet widespread. Therefore, the current technologies such as Multi-chip Package (MCP), Stack Die, and Package on Package ; PoP), PiP (Package in Package), embedded substrate (Embedded Substrate) and other technologies are mainstream technologies in the industry

[0005] The above-mentioned system-in-package technology such as MCP and other technologies integrate multiple ICs into one package. However, the ICs before integration are usually not all known good dies. It is necessary to integrate all ICs. Facing the complex testing process before and after integration and the problem of heat dissipation, what's more, when any IC fails, the 3D IC can only be scrapped as a whole

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