Semiconductor structure and formation method thereof
A semiconductor and gate structure technology, applied in the field of semiconductor structure and its formation, can solve the problems of high process cost, long process time, complex manufacturing process, etc., and achieve the effects of shortening process time, reducing process cost and simplifying the formation process
Active Publication Date: 2015-02-11
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0006] However, for CMOS transistors composed of fin field effect transistors, stress layers respectively in the first fin portion 103 and the second fin portion 104 are required, the manufacturing process is complicated, the process cost is high, and the process time is long
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[0031] As mentioned in the background, for the existing CMOS transistors composed of fin field effect transistors, the process of forming the stress layer in the PMOS transistor and the NMOS transistor is relatively complicated.
[0032] Please continue to refer figure 1In the prior art, the method for forming a stress layer in a CMOS transistor composed of a FinFET transistor includes: forming a first mask layer on the surface of the second fin portion 103, the second gate structure 105 and part of the dielectric layer 101, so The first mask layer exposes the top and sidewall surfaces of the first fins 102 on both sides of the first gate structure 104; using the first mask layer as a mask, a selective epitaxial deposition process is used to deposit 102 The exposed top and sidewall surfaces form a first stress layer, the material of the first stress layer is silicon germanium; after the first stress layer is formed, the first mask layer is removed; after the first mask layer i...
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The invention relates to a semiconductor structure and a formation method thereof. The semiconductor structure formation method comprises steps that a substrate has a first region and a second region, the substrate surface of the first region has a first fin portion, a side wall and the top surface of the first fin portion have first grid electrode structures, the substrate surface of the second region has a second fin portion, and a side wall and the top surface of the second fin portion have second grid electrode structures; a mask layer is formed at the second region; after the mask layer is formed at the second region, first semiconductor layers are formed at first fin portion surfaces at two sides of the first grid electrode structures, and the crystal face index of any surface of the first semiconductor layers is respectively (111); the mask layer is etched to expose the top surface of the second fin portion; second semiconductor layers are formed at the top surface of the second fin portion and the first semiconductor layer surfaces, and width of the second semiconductor layers on the first semiconductor layer surfaces is smaller than width of the second semiconductor layer on the top surface of the second fin portion. The semiconductor structure formation method is simplified.
Description
technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase of component density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter. The ability of traditional planar transistors to control channel current Weakened, resulting in short channel effect, resulting in leakage current, and ultimately affecting the electrical performance of semiconductor devices. [0003] In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a fin field effect tra...
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IPC IPC(8): H01L21/8238H01L27/092H01L29/04
CPCH01L21/823821H01L27/0924H01L29/045
Inventor 洪中山
Owner SEMICON MFG INT (SHANGHAI) CORP