Flip chip packaging method and packaging substrate

Abstract

The invention provides a packaging method and a packaging substrate for a flip chip. The packaging substrate comprises a substrate, substrate welding pads and substrate convex blocks, wherein the substrate is provided with a plurality of welding areas, each substrate welding pad is positioned on the corresponding welding area, and the each substrate convex block is positioned on the corresponding substrate welding pad. The packaging substrate has the advantage that the packaging substrate is provided with the substrate convex blocks, the substrate convex blocks are used for welding a wafer convex block on a wafer, and the thinner wafer convex block can be manufactured when the flip chip is packaged by the packaging substrate, so the overflow of the wafer convex block in the manufacturing process is avoided, the short-circuiting of the adjacent wafer convex blocks is avoided when the wafer convex blocks and the packaging substrate are welded together, namely, the bridging condition of the convex blocks is avoided.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a flip chip packaging method and packaging substrate. Background technique [0002] Semiconductor packaging refers to the process of processing wafers according to product models and functional requirements to obtain independent chips. Existing semiconductor packages include wire-bonding packages and flip-chip packages. Compared with the wire bonding packaging method, the flip chip packaging method has the advantages of high packaging density, excellent heat dissipation performance, high input / output (I / O) port density and high reliability. [0003] The earlier flip-chip packaging method used the die bumps arranged on the die pads (including input / output pads) to solder to the packaging substrate, and the die pads and die bumps were located in the pad area superior. With the development of the semiconductor industry in the direction of miniaturization, there are multiple...

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Problems solved by technology

[0005] However, with the further increase of semiconductor integration density, the distance between wafer bumps is further reduced. Even in the existing flip-chip packaging method that introduces interconnection copper pillar technology, adjacent wafers still appear. The original bump is short-circuited, that is, the problem of bump bridging occurs. It can be seen that the existing flip-chip packaging technology has been unable to avoid the problem of bump bridging.

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