How to check layout graphics
An inspection method and graphics technology, applied to the photolithographic plate-making process of the pattern surface, the original for photomechanical processing, optics, etc., can solve the problem of lithographic graphics yield to be improved, low accuracy, increased manufacturing costs, etc. problem, to achieve the effect of increasing yield, improving accuracy and reducing production cost
Active Publication Date: 2018-07-10
SEMICON MFG INT (SHANGHAI) CORP
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[0006] In the prior art, when using the photomask pattern initially meeting the requirements for actual layout pattern inspection, multiple modifications are still required to obtain the final photomask pattern design. The potential defects found in the prior art The accuracy rate is not high, that is, the yield rate of forming the actual photolithography pattern after exposure and development using the photomask template with the design photomask pattern that initially meets the requirements still needs to be improved, which greatly increases the manufacturing cost
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[0025] As mentioned in the background art, in the prior art, when using the preliminary design photomask pattern for actual layout pattern inspection, it still needs to undergo multiple modifications before obtaining the final design photomask pattern, that is, using the The yield rate of the actual photolithography pattern formed after exposure and development of the photomask template with the designed photomask pattern that meets the requirements still needs to be improved, which greatly increases the manufacturing cost.
[0026]After analysis, the existing technology compares the distance between each point of the simulated lithography pattern and each point on the corresponding target pattern one by one to find out the potential defect point (potential weak point), the premise of which is The OPC model used to simulate lithographic patterns is accurate. Although the OPC model was established after a large number of experiments and repeated demonstrations, the model may ha...
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The invention discloses a layout graph checking method which comprises the following steps: providing a target graph and an optical lens system, and providing an original photomask pattern designed according to the target graph and the optical lens system; acquiring parameters of an original photomask pattern and an original optical lens, performing first modeling on the original photomask pattern according to the parameters of the optical lens system, and acquiring the spatial light intensity which corresponds to each point on the original photomask pattern; acquiring lithography parameters, performing second modeling on the spatial light intensity according to the lithography parameters, and acquiring the lithography light intensity which corresponds to each point on the original photomask pattern; and comparing the spatial light intensity and the lithography light intensity of each point on the original photomask pattern one by one, acquiring the difference value of the spatial light intensity and the lithography light intensity, and marking the point on the original photomask pattern when the difference value is greater than a first preset value. According to the method, the accuracy rate of the found potential defect point is improved. Therefore, an accurate designed photomask pattern which preliminarily meets the requirement can be obtained.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for inspecting layout patterns. Background technique [0002] In the semiconductor manufacturing process, the photolithography process plays a central role and is the most important process step in the production of integrated circuits. With the development of semiconductor manufacturing technology, the feature size is getting smaller and smaller, and the requirements for resolution in lithography technology (the minimum feature size that can be exposed on the surface of a silicon wafer by a lithography machine) are getting higher and higher. [0003] In order to achieve tiny lithographic resolution, it is necessary to focus finer images on the photomask on the photoresist, and to enhance the lithographic resolution to manufacture semiconductor devices approaching the lithographic resolution limit in the photomask process . Resolution enhancement techniques incl...
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IPC IPC(8): G03F1/36
CPCG03F1/36G03F1/84
Inventor 王辉李天慧
Owner SEMICON MFG INT (SHANGHAI) CORP