A kind of NDC growth control method

Abstract

The invention relates to the field of semiconductor device manufacturing, in particular to an NDC growth control method. After the wafer acceptance test engineer specifies the maximum needle penetration capability of the probe card, the engineer can input the NDC generation thickness range to be confirmed, and return the available time of the wafer acceptance test time under the condition that no void defect occurs through regression analysis, and at the same time Engineers can perform reliability verification through the provided sensitivity analysis method, and carry out wafer acceptance test scheduling control based on the provided data, which can not only avoid process defects, but also improve wafer acceptance test capabilities and work efficiency.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to an NDC growth control method. Background technique [0002] In recent years, semiconductor wafer manufacturing process equipment in semiconductor wafer manufacturing plants, hereinafter referred to as "FAB", usually uses doped silicon carbide film (Nitride Doped Silicon Carbide, referred to as NDC) as a dielectric barrier layer, the purpose of which is to A dielectric barrier is used to prevent the diffusion of metal into the dielectric. [0003] After the wafer is prepared, a WAT ​​(Wafer Acceptance Test, Wafer Acceptance Test) process usually needs to be performed, that is, the electrical parameters of each chip on the wafer are measured by sticking a probe. However, due to various objective conditions, it is necessary to arrange the test Lot (batch) before the measurement, causing the Q-Time time (Queue Time, ie waiting time) of some Lot to be too long. If t...

AI Technical Summary

Problems solved by technology

However, due to various objective conditions, it is necessary to arrange the test Lot (batch) before the measurement, causing the Q-Time time (Queue Time, that is, waiting time) of some Lot to be too long

If the NDC growth thickness is not enough, it will cause a large number of void defects after being exposed for too long, and the surface of the wafer cannot be completely covered, forming voids

However, if the NDC growth thickness is too thick, it will lead to the failure of the WAT test. Since the optimal value of the NDC growth thickness cannot be accurately judged, FAB needs to provide a lot of manpower and material resources for slicing experiments, which greatly reduces the process capability and FAB production capacity.

[0004] In the existing NDC process, the NDC growth thickness can only be analyzed through the experience of engineers, and whether the NDC thickness is usable can be judged through a large number of slice experiments: for example, when the WATQ-Time time is too long, whether there will be void defects due to the thin NDC thickness, Or needle failure due to excessive thickness of NDC

However, this method greatly reduces the process capability and FAB production capacity

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