Embedded Gate Insulated Tunneling Enhancement Transistor

Abstract

The invention relates to a high-transfer characteristic and low parasitic capacitance built-in gate insulation tunneling enhanced transistor. Compared with MOSFETs or TFETs of the same size, the extremely sensitive relationship between the impedance of the tunneling insulating layer and the electric field intensity in the tunneling insulating layer is used to realize a more sensitive relationship. Good transfer characteristics; avoiding the obvious increase of parasitic capacitance between gate-source, source-gate, gate-drain and drain-gate due to the shrinking distance between gate electrode and drain electrode or between gate electrode and source electrode, making The device significantly reduces parasitic capacitance while ensuring high transfer characteristics; and since there is no gate-to-drain overlap region that MOSFETs or TFETs have, it does not cause significant reverse leakage current. The invention also proposes a specific manufacturing method of an embedded gate insulation tunneling enhancement transistor with high transfer characteristics and low parasitic capacitance. The transistor significantly improves the working characteristics of the nanoscale integrated circuit unit and is suitable for popularization and application.

Description

[0001] Technical field: [0002] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to an embedded gate insulation tunneling enhanced transistor with high transfer characteristics and low parasitic capacitance, which is suitable for the manufacture of high-performance ultra-high integrated integrated circuits. [0003] Background technique: [0004] Currently, the ever-shortening device channel lengths of integrated circuit unit metal-oxide-semiconductor field-effect transistors (MOSFETs) have resulted in degraded device transfer characteristics. The subthreshold swing increases with decreasing channel length, and the static power consumption increases significantly. Although the degradation of the device performance can be alleviated by improving the structure of the gate electrode, when the device size is further reduced, the transfer characteristics of the device will deteriorate again. [0005] On the other hand, with the ...

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Problems solved by technology

Although the degradation of this device performance can be alleviated by improving the structure of the gate electrode, when the device size is further reduced, the transfer characteristics of the device will deteriorate again

[0005] On the other hand, with the continuous reduction of device size, the distance between the drain electrode and the gate electrode, or the distance between the source electrode and the gate electrode is also continuously reduced, which makes the gate-source, source-gate of the device , Gate-to-drain and drain-gate parasitic capacitance increases significantly, which increases the power consumption of the integrated circuit, increases the signal propagation delay and negative feedback, and affects the gain-bandwidth product

[0006] Tunneling Field Effect Transistors (TFETs), compared with the transfer characteristics of MOSFETs, although its average subthreshold swing has been improved, but its forward conduction current is too small, and the parasitic capacitance generated due to size reduction, compared with MOSFETs and no improvement

[0007] The tunneling part of TFETs can be generated by introducing materials with narrower band gaps such as compound semiconductors, silicon germanium or germanium, which can increase the tunneling probability and improve the transfer characteristics, but increases the production cost and increases the difficulty of the process.

In addition, the use of high dielectric constant insulating material as the insulating dielectric layer between the gate and the substrate can improve the control ability of the gate to the electric field distribution of the channel, but it cannot substantially increase the tunneling probability of the silicon material, so Limited improvement in transfer characteristics for TFETs

[0008] In addition, since both TFETs and MOSFETs control the electric field, potential and carrier distribution inside the gate insulating layer and semiconductor through the electric field effect of the gate electrode, in order to improve the control ability of the gate electrode to the inside of the semiconductor, high dielectric The constant and thinning gate insulating layer strengthens the control ability of the gate electrode, but at the same time shortens the distance between the gate electrode and the drain region, the gate electrode and the source region, so that the overlapping area of ​​the gate electrode and the drain electrode is at the gate electrode Larger gate-induced-drain leakage (GIDL) or gate-induced-source leakage (GISL) currents are generated when extremely reverse biased

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