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Folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor and manufacturing method of folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor

A saddle-shaped, transistor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of large gate to source, no improvement in parasitic capacitance characteristics, shortening distance, etc., and achieve low parasitic capacitance characteristics Effect

Inactive Publication Date: 2015-03-25
SHENYANG POLYTECHNIC UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although the degradation of this device performance can be alleviated by improving the structure of the gate electrode, when the device size is further reduced, the switching characteristics of the device will continue to deteriorate
[0004] Compared with MOSFETs, tunneling field effect transistors (TFETs) proposed in recent years, although their average subthreshold swing has been improved, but their forward conduction current is too small, and the characteristics of parasitic capacitance generated under the same size are not the same. improve
[0005] In addition, TFETs can be formed as the tunneling part of TFETs by introducing materials with narrower band gaps such as compound semiconductors, silicon germanium or germanium, which can increase the tunneling probability to improve switching characteristics, but increases the difficulty of the process
Using a high dielectric constant insulating material as the insulating dielectric layer between the gate and the substrate can improve the control ability of the gate to the electric field distribution of the channel, but it cannot essentially increase the tunneling probability of silicon materials. Therefore, for TFETs The forward conduction characteristic of the improvement is very limited
[0006] In addition, since both TFETs and MOSFETs control the electric field, potential and carrier distribution inside the gate insulating layer and semiconductor through the electric field effect of the gate electrode, in order to improve the control ability of the gate electrode to the inside of the semiconductor, high dielectric The constant and thinning gate insulating layer strengthens the control ability of the gate electrode, but at the same time shortens the distance between the gate electrode and the drain region, the gate electrode and the source region, so that the overlapping area of ​​the gate electrode and the drain electrode is at the gate electrode Larger gate-induced-drain leakage (GIDL) or gate-induced-source leakage (GISL) currents are generated when extremely reverse biased

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  • Folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor and manufacturing method of folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor
  • Folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor and manufacturing method of folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor
  • Folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor and manufacturing method of folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor

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Embodiment Construction

[0099] Below in conjunction with accompanying drawing, the present invention will be further described: figure 1 A three-dimensional structural schematic diagram after stripping off the emitter 9, the collector 10 and the blocking insulating layer 11 for the embedded folded gate saddle-shaped insulating tunneling enhancement transistor of the present invention; figure 2 A three-dimensional structural schematic diagram after stripping off the emitter 9, the collector 10, the blocking insulating layer 11, the emitter region 3, the base region 4 and the collector region 5 for the embedded folded gate saddle-shaped insulation tunneling enhancement transistor of the present invention; image 3 The three-dimensional structure after the emitter 9, the collector 10, the blocking insulating layer 11, the emitter region 3, the base region 4, the collector region 5 and the saddle-shaped conductive layer 6 are removed for the embedded folded gate saddle-shaped insulating tunneling enhance...

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Abstract

The invention relates to a folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor. Compared with MOSFETs or TFETs devices in the same size, the folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor has the advantages of low stray capacitance and low reverse leakage current. The excellent switching characteristic is achieved through the quite-sensitive mutual relation between impedance of a tunneling insulating layer and the internal field intensity of the tunneling insulating layer; tunneling signals are enhanced through an emitting electrode to achieve the excellent forward-direction breakover characteristic. In addition, the invention further provides a specific manufacturing method for the folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor and an array of the folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor. By means of the folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor, the operating characteristic of a nanometer-grade integrated circuit unit is obviously improved; the folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor is suitable for application and popularization.

Description

Technical field: [0001] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a structure and a manufacturing method of an embedded folded-gate saddle-shaped insulation tunneling enhancement transistor suitable for manufacturing high-performance ultra-high-integrated integrated circuits. Background technique: [0002] Currently, as the device size of metal-oxide-semiconductor field-effect transistors (MOSFETs), the basic unit of integrated circuits, continues to shrink, the distance between the drain electrode and the gate electrode, or the distance between the source electrode and the gate electrode, is also continuously reduced. Small, this will significantly increase the gate-source, source-gate, gate-drain and drain-gate parasitic capacitance of the device, increase the power consumption of the integrated circuit, increase the propagation delay and negative feedback of the signal, and affect the gain-bandwidth product . ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/739H01L29/423H01L29/10H01L21/28H01L21/331
CPCH01L21/28H01L29/10H01L29/4232H01L29/66477H01L29/78
Inventor 靳晓诗吴美乐刘溪揣荣岩
Owner SHENYANG POLYTECHNIC UNIV
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