Groove embedded grid insulating tunneling enhanced transistor and manufacturing method thereof

Abstract

The invention relates to a groove embedded grid insulating tunneling enhanced transistor. Compared with MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) or TFETs (Tunneling Field-Effect Transistor) devices of the same size, the adopted design scheme has the advantage that low parasitic capacitance and low reverse leakage current are realized on the premise that the chip area is not increased. Superior switching characteristic is realized by using the extremely sensitive mutual relation between the impedance of a tunneling insulating layer and the field intensity in the tunneling insulating layer; superior forward turn-on characteristic is realized by enhancing a tunneling signal through an emitter electrode; compared with a normal planar structure, the transistor has the advantage of avoiding that an emitter region, a base region and a collector region are arranged along the horizontal direction in sequence, so that the chip area is saved, and higher integration can be realized. Besides, the invention also provides a specific manufacturing method of the groove embedded grid insulating tunneling enhanced transistor. According to the transistor, the working characteristic of a nanoscale integrated circuit unit is obviously improved; the transistor is suitable for popularization and application.

Description

Technical field: [0001] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a gate-insulated tunneling enhancement transistor embedded in a groove and a manufacturing method thereof, which are suitable for manufacturing high-performance ultra-high-integrated integrated circuits. Background technique: [0002] Currently, as the device size of metal-oxide-semiconductor field-effect transistors (MOSFETs), the basic unit of integrated circuits, continues to shrink, the distance between the drain electrode and the gate electrode, or the distance between the source electrode and the gate electrode, is also continuously reduced. Small, this will significantly increase the gate-source, source-gate, gate-drain and drain-gate parasitic capacitance of the device, increase the power consumption of the integrated circuit, increase the propagation delay and negative feedback of the signal, and affect the gain-bandwidth product . [000...

AI Technical Summary

Problems solved by technology

Although the degradation of this device performance can be alleviated by improving the structure of the gate electrode, when the device size is further reduced, the switching characteristics of the device will continue to deteriorate

[0004] Compared with MOSFETs, tunneling field effect transistors (TFETs) proposed in recent years, although their average subthreshold swing has been improved, but their forward conduction current is too small, and the characteristics of parasitic capacitance generated under the same size are not the same. improve

[0005] In addition, TFETs can be formed as the tunneling part of TFETs by introducing materials with narrower band gaps such as compound semiconductors, silicon germanium or germanium, which can increase the tunneling probability to improve switching characteristics, but increases the difficulty of the process

Using a high dielectric constant insulating material as the insulating dielectric layer between the gate and the substrate can improve the control ability of the gate to the electric field distribution of the channel, but it cannot essentially increase the tunneling probability of silicon materials. Therefore, for TFETs The forward conduction characteristic of the improvement is very limited

[0006] In addition, since both TFETs and MOSFETs control the electric field, potential and carrier distribution inside the gate insulating layer and semiconductor through the electric field effect of the gate electrode, in order to improve the control ability of the gate electrode to the inside of the semiconductor, high dielectric The constant and thinning gate insulating layer strengthens the control ability of the gate electrode, but at the same time shortens the distance between the gate electrode and the drain region, the gate electrode and the source region, so that the overlapping area of ​​the gate electrode and the drain electrode is at the gate electrode Larger gate-induced-drain leakage (GIDL) or gate-induced-source leakage (GISL) currents are generated when extremely reverse biased

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