Insulated gate insulated tunneling enhanced transistor embedded in groove and manufacturing method thereof

Abstract

The invention relates to a gate insulation tunneling enhancement transistor embedded in a groove. Compared with MOSFETs or TFETs devices of the same size, the design scheme adopted realizes the advantages of low parasitic capacitance and low reverse leakage current without increasing the chip area. . Using the extremely sensitive relationship between the impedance of the tunneling insulating layer and its internal field strength to achieve excellent switching characteristics; the tunneling signal is enhanced through the emitter to achieve excellent forward conduction characteristics; compared with ordinary planar structures, it avoids the emission area, The base area and the collector area are arranged in sequence along the horizontal direction, thus saving chip area and achieving higher integration. In addition, the present invention also proposes a specific manufacturing method of an insulated gate-insulated tunneling enhancement transistor embedded in a groove. The transistor significantly improves the working characteristics of the nanoscale integrated circuit unit and is suitable for popularization and application.

Description

Technical field: [0001] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a gate-insulated tunneling enhancement transistor embedded in a groove and a manufacturing method thereof, which are suitable for manufacturing high-performance ultra-high-integrated integrated circuits. Background technique: [0002] Currently, as the device size of metal-oxide-semiconductor field-effect transistors (MOSFETs), the basic unit of integrated circuits, continues to shrink, the distance between the drain electrode and the gate electrode, or the distance between the source electrode and the gate electrode, is also continuously reduced. Small, this will significantly increase the gate-source, source-gate, gate-drain and drain-gate parasitic capacitance of the device, increase the power consumption of the integrated circuit, increase the propagation delay and negative feedback of the signal, and affect the gain-bandwidth product . [000...

AI Technical Summary

Problems solved by technology

Although the degradation of this device performance can be alleviated by improving the structure of the gate electrode, when the device size is further reduced, the switching characteristics of the device will continue to deteriorate

[0004] Compared with MOSFETs, tunneling field effect transistors (TFETs) proposed in recent years, although their average subthreshold swing has been improved, but their forward conduction current is too small, and the characteristics of parasitic capacitance generated under the same size are not the same. improve

[0005] In addition, TFETs can be formed as the tunneling part of TFETs by introducing materials with narrower band gaps such as compound semiconductors, silicon germanium or germanium, which can increase the tunneling probability to improve switching characteristics, but increases the difficulty of the process

Using a high dielectric constant insulating material as the insulating dielectric layer between the gate and the substrate can improve the control ability of the gate to the electric field distribution of the channel, but it cannot essentially increase the tunneling probability of silicon materials. Therefore, for TFETs The forward conduction characteristic of the improvement is very limited

[0006] In addition, since both TFETs and MOSFETs control the electric field, potential and carrier distribution inside the gate insulating layer and semiconductor through the electric field effect of the gate electrode, in order to improve the control ability of the gate electrode to the inside of the semiconductor, high dielectric The constant and thinning gate insulating layer strengthens the control ability of the gate electrode, but at the same time shortens the distance between the gate electrode and the drain region, the gate electrode and the source region, so that the overlapping area of ​​the gate electrode and the drain electrode is at the gate electrode Larger gate-induced-drain leakage (GIDL) or gate-induced-source leakage (GISL) currents are generated when extremely reverse biased

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