Digital FNPLL (Fractional-N Phase-Locked Loop) control method and PLL (Phase-Locked Loop)

A technology of fractional frequency division and phase-locked loop, applied in the field of electronics

Active Publication Date: 2015-04-08
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there is usually a relatively close compromise between range and accuracy, and it is often difficult to meet the requirements of the above two dimensions

Method used

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  • Digital FNPLL (Fractional-N Phase-Locked Loop) control method and PLL (Phase-Locked Loop)
  • Digital FNPLL (Fractional-N Phase-Locked Loop) control method and PLL (Phase-Locked Loop)
  • Digital FNPLL (Fractional-N Phase-Locked Loop) control method and PLL (Phase-Locked Loop)

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Embodiment Construction

[0086] image 3 A schematic structural diagram of a digital fractional frequency-division phase-locked loop provided in Embodiment 1 of the present invention, as shown in image 3 As shown, the phase-locked loop includes a control device and a time-to-digital converter TDC, a digital loop filter DLF, a digitally controlled oscillator DCO, a feedback frequency divider DIV and a Sigma-Delta modulator SDM.

[0087] Wherein, the output end of the control device is connected to the first input end of the TDC; the output end of the TDC is connected to the input end of the DLF, the output end of the DLF is connected to the input end of the DCO, and the output end of the DCO is connected to the first input end of the DIV ; The output end of DIV is connected with the second input end of TDC; The second input end of DIV is connected with the output end of SDM, the first input end of the control device is connected with the output end of SDM, the second input end of the control device is...

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Abstract

The embodiment of the invention provides a digital FNPLL (Fractional-N Phase-Locked Loop) control method and a PLL (Phase-Locked Loop). The PLL comprises a control device, a TDC (Time-to-Digital Converter), a DLF (Digital Loop Filter), a DCO (Digital Controlled Oscillator), a DIV (Frequency Divider) and an SDM (Sigma-Delta Modulator), wherein the control device is used for carrying out delay processing on an effective edge of a reference clock according to a frequency control word and a fractional frequency control word to obtain a delayed reference clock; the delayed reference clock is sent to the TDC for enabling the TDC to carry out phase detection processing on the delayed reference clock and a feedback clock. According to the PLL provided by the invention, the control device which is additionally arranged in the PLL can be used for carrying out the delay processing on the reference clock according to the current frequency control word and the fractional frequency control word, so that the feedback clock and the delayed reference clock are enabled to have similar effective edge corresponding time, the TDC just needs to process phase detection signals in a very small time-domain input range, the design difficulty of the TDC and the needs on the resolution rate of the TDC are greatly reduced, the design of the TDC can be simple and free, and the design DOF (Degree Of Freedom), the simplicity and the effectiveness of the PLL are ensured.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a digital fractional frequency division phase-locked loop control method and the phase-locked loop. Background technique [0002] In radio frequency transceivers, a frequency synthesizer based on a Phase-Locked Loop (PLL) structure is widely used to generate a local oscillator signal, referred to as a local oscillator signal, to complete a frequency shift operation of a data signal. [0003] In a wireless communication system, especially in a wireless terminal, due to factors such as cost, a Zero Intermediate-Frequency (ZIF) radio frequency transceiver architecture is widely used. In a radio frequency transceiver of this type of architecture, no matter it is a signal transmitting channel or a signal receiving channel, it is required that the frequency of the local oscillator signal is exactly the same as that of the radio frequency carrier frequency signal. That ...

Claims

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Application Information

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IPC IPC(8): H03L7/18
CPCH03L7/085H03L7/1976H03L7/081H03L7/091H03L7/0992H03L7/1974
Inventor 高鹏
Owner HUAWEI TECH CO LTD
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