A method of manufacturing a semiconductor device

Abstract

The invention relates to a method for manufacturing a semiconductor device. The method comprises the following steps: providing a semiconductor substrate; forming a front layer on the semiconductor substrate; successively forming a thin oxide layer and a high-etching-rate bottom antireflective coating on the front layer; forming a patterned photoresist layer on the high-etching-rate bottom antireflective coating; according to the patterned photoresist layer, etching the high-etching-rate bottom antireflective coating so as to form an opening exposing the thin oxide layer; removing the patterned photoresist layer; and removing the exposed thin oxide layer. According to the invention, in the manufacture process of the semiconductor device, the high-etching-rate bottom antireflective coating and the thin oxide layer are formed on the substrate, such that the problem of reflection of the substrate when an injection photoetching process is carried out is solved, the problem of damage caused to the front layer and the substrate is avoided, and the performance of the device is improved.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing process, in particular, the present invention relates to an implantlithography (Implantlithography) process. Background technique [0002] Integrated circuits (ICs) have grown from a handful of interconnected devices fabricated on a single silicon chip to millions of devices. Current ICs offer performance and complexity far beyond what was originally imagined. To achieve improvements in complexity and circuit density (i.e., the number of devices that can be packed into a given chip area), the size of the smallest device feature, also known as device "geometry," has become smaller with each IC generation. Small. Semiconductor devices are now fabricated with features that span less than a quarter of a micron. [0003] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integr...

AI Technical Summary

Problems solved by technology

However, TARC and DBARC have limited performance

The use of OPC bias rules is very complicated, which increases the complexity of the process

It is also proposed to use the traditional BARC process in the implant lithography process. However, the damage problem of the pre-layer film will be generated in the etching step. Therefore, the traditional BARC process cannot be applied to the implant layer (Implant layer)

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