Flash memory and how to operate it

Abstract

The invention discloses a flash memory. A power supply voltage supplies power to the flash memory. The flash memory array structure of the flash memory is composed of a plurality of flash memory unit structures. The flash memory cell structure includes a first source and drain region and a second source and drain region. A first control gate, a word line gate and a second control gate are formed above the surface of the channel region. The first control gate and the second control gate Each includes a floating gate for storing charge information, and the first control gate and the second control gate have a symmetrical structure on both sides of the word line gate. When a flash memory cell structure in a flash memory array structure is read, the bit lines that have not been read are connected to the power supply voltage. The parasitic capacitance of the bit lines that have not been read forms the decoupling capacitor of the power supply voltage. Decoupling capacitors remove noise interference from the supply voltage. The invention also discloses an operating method of the flash memory. The present invention does not need to increase the area of ​​an additional decoupling capacitor for the power supply voltage, thereby reducing the area of ​​the entire flash memory chip and reducing the chip cost.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a flash memory (Flash); the invention also relates to a method for operating the flash memory. Background technique [0002] Such as figure 1 Shown is a schematic diagram of the flash memory array structure of the existing flash memory; figure 2 Shown is a schematic diagram of the flash memory unit structure of the existing flash memory. The flash memory array structure 100 is composed of a plurality of flash memory cell structures 101 arranged in arrangement. Taking the flash memory cell structure 101 located in the first row and the first column as an example, the description is as follows: the flash memory cell structure 101 includes a first source-drain region 102a and a second source-drain region 102b composed of N+ doped regions, the first Between the source and drain region 102a and the second source and drain region 102b is a P-type doped ...

AI Technical Summary

Problems solved by technology

During the read operation of the flash memory, the noise existing on the power supply voltage VDD will affect the read speed and accuracy. In order to improve the read performance, the power supply voltage VDD needs to be decoupled. At this time, an additional decoupling capacitor Cd is required.

Since an additional decoupling capacitor Cd needs to be added separately in the prior art, this will cause a waste of area and increase the cost of the chip

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