Technology integration method of fin field-effect transistor

Abstract

The invention discloses a technology integration method of a fin field-effect transistor. After side wall etching and core layer removing in a fin layer patterning technology process, a barrier photoetching model is additionally adopted for performing a photoetching technology, and a virtual pattern for improving the planarization of a fin layer insulating layer, fin layer patterns different from a non-photoresist pattern region in width, a protecting pattern for measuring marks and other patterns contained in the barrier photoetching model are utilized to increase the density of final fin layer patterns, improve the flexibility of fin layer layout design and obtain the fin layer patterns different in width. Thus, on the premise of limited cost increase, multiple devices can be manufactured on a silicon wafer substrate, the uniformity of a follow-up fin layer insulating layer planarization technology and the uniformity of fin layer etching can be improved, and the film thickness measuring marks can be protected.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, and more specifically, to a process integration method for fin field effect transistors. Background technique [0002] Fin Field Effect Transistor (FinFET) technology is the next frontier in the integrated circuit industry. FinFET is a brand-new multi-gate three-dimensional transistor, and its active layer is also called fin layer. In the patterning process of the FinFET fin layer, due to the characteristics of the design rules and the limitation of the resolution of the lithography machine, two photolithography plates and two photolithography processes are generally used, and the side wall hard mask is used to automatically Align patterning technology and line end cutting patterning technology to form the final fin layer patterning process. [0003] However, the process of patterning the fin layer by self-alignment patterning of the sidewall hard mask has the following...

AI Technical Summary

Problems solved by technology

[0003] However, the fin layer patterning process using the side wall hard mask self-aligned patterning has the following disadvantages: first, the formed fin layer pattern has a single size

Therefore, different device channel widths cannot be defined by changing the width of the fin layer, or different devices can only be defined by changing the number of fins

This places high demands on the design rules and also limits the flexibility of the device

Second, because the thickness of the sidewall hard mask is very thin, the width of the formed fin layer pattern is very small, and no matter the size of the core layer pattern area, the final pattern can only be left in the area of ​​the peripheral sidewall

Therefore, the pattern density formed by the side wall hard mask is very low, which is not conducive to the etching of the target layer of the fin layer and the planarization process after the deposition of the insulating layer of the fin layer.

Third, sidewall hard mask self-aligned patterning techniques can destroy markings for in-line monitoring and measurement

For example, thickness measurement marks, etc., require large graphics with a certain area. However, after the fin layer patterning process, only the graphics in the area where the side walls are located are left, and there are no large graphics with a certain area, so online thickness monitoring cannot be performed.

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