Coplanar electrode analog photoelectric detector chip and manufacturing method thereof

Abstract

The invention discloses a coplanar electrode analog photoelectric detector chip and a manufacturing method thereof. The coplanar electrode analog photoelectric detector chip comprises an epitaxial wafer and an ohm contact layer formed on the rear surface of the epitaxial wafer; the epitaxial wafer comprises a substrate, a buffer layer, an absorption layer, a transition layer, a top layer, a passivation layer, a doped photosensitive area, a limiting channel, an antireflective transition film layer, a P-type electrode metal layer and an N-type electrode metal layer; the top layer is a n-type III-V top layer with at least three elements; the doped photosensitive area is circular; the limiting channel is semi-circular and surrounds the doped photosensitive area. The manufacturing method of the coplanar electrode analog photoelectric detector chip is simple in process and high in finished product rate; the coplanar electrode analog photoelectric detector chip manufactured by the method has the characteristics of low distortion, low dark current, high linearity, high responsibility, high reliability and the like.

Description

technical field [0001] The invention relates to the technical field of optical communication, in particular to a coplanar electrode analog photodetector chip and a manufacturing method thereof. Background technique [0002] In general, photodetector chips can be divided into two categories: digital photodetector chips and analog photodetector chips. Analog photodetector chips are mainly used in fiber optic CATV (Community Antenna Television) receiving systems and fiber optic FTTP (Fiber To The Premise) receiving systems. Compared with conventional digital detector chips, the main feature of analog photodetector chips is that they require low combined second-order distortion and third-order intermodulation distortion, and require high linearity, high responsivity and low dark current. In order to achieve low distortion, the chip needs to be fully depleted at the lowest possible reverse bias voltage to ensure that the chip capacitance changes as little as possible with the in...

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Problems solved by technology

The mesa structure will inevitably face the following problems: 1. Difficult surface passivation and large dark current; 2. Low ESD threshold; 3. Poor reliability, and open circuits often occur on the electrodes at climbing places; 4. The manufacturing process is difficult , long process, poor repeatability; 5, low yield; 6, high production cost

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