Restoring circuit for lowering negative bias temperature instability of level switching circuit

Abstract

The invention provides a restoring circuit for lowering the negative bias temperature instability of a level switching circuit. The restoring circuit comprises a level switching circuit and an NBTI effect restoring unit, wherein the level switching circuit mainly consists of a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a first inverter INV1; the NBTI effect restoring unit mainly consists of a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a second inverter INV2 and a restoring signal input terminal RM. Through the adoption of the technical scheme of the restoring circuit provided by the invention, the negative drift of threshold voltages of PMOS tubes is effectively inhibited, the performance and the reliability of the level switching circuit are improved, the current leakage is effectively inhibited, and the static power consumption of the level switching circuit is lowered.

Description

technical field [0001] The invention relates to the field of semiconductor memory, in particular to a recovery circuit for improving the temperature instability of the negative bias voltage of a level conversion circuit. Background technique [0002] With the increasing integration of semiconductor memory integrated circuits, the requirements for transistor performance are also increasing. Therefore, the requirements for the reliability of transistors are also increased. In the CMOS process, the negative gate temperature instability (NBTI) will greatly affect the working stability of the PMOS. [0003] The NBTI (negative bias temperature instability) effect occurs in PMOS devices. When the gate of the device is under negative bias, the saturated drain current Idsat and transconductance Gm of the device decrease continuously, and the absolute value of the threshold voltage increases continuously. This NBTI effect, which degrades device performance, becomes more pronounced...

AI Technical Summary

Problems solved by technology

Since the source of one of the two PMOS transistors 101 and 102 is connected to the high-voltage signal terminal VPP and the gate is connected to the low-level 0V during normal operation, there is a large voltage difference VPP between the gate and the source. In this case, the PMOS transistor will experience a more serious NBTI effect during normal operation, which will directly affect the performance and service life of the PMOS transistor, and eventually cause the entire level shifting circuit to fail to work normally.

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