Transistor manufacturing method and transistor

Abstract

The present invention provides a transistor manufacturing method and a transistor, wherein the transistor manufacturing method includes: growing a second oxide layer on the surface of the substrate on which the first oxide layer and the first base region are formed, the second oxide layer is located on the first above the base region; an emission region is formed in a first predetermined region on the second oxide layer; a contact hole is formed in a second predetermined region on the second oxide layer, wherein the second predetermined region is the same as the first predetermined region not intersecting; implanting doping elements into the surface layer of the first base region in the contact hole region; performing heat treatment on the substrate to activate the doping elements to form the second base region. The invention can skillfully integrate the photoresist layer of the concentrated base region and the photoresist layer of the contact hole, realize the self-alignment relationship between the photoresist layer of the concentrated base region and the photoresist layer of the contact hole, and solve the problem of the photoresist layer of the concentrated base region and the contact hole photoresist layer. Alignment misalignment of contact holes.

Description

technical field [0001] The invention relates to the technical field of semiconductor device manufacturing, in particular to a transistor manufacturing method and a transistor manufactured by the transistor manufacturing method. Background technique [0002] With the development of radio frequency and wireless communication technology, high frequency transistors are used more and more. High-frequency transistors in a broad sense include high-frequency bipolar transistors and high-frequency field-effect transistors. frequency bipolar transistor). [0003] The most important parameter to measure the performance of high-frequency transistors is its operating frequency. In order to increase the operating frequency of high-frequency transistors, a comb-like strip structure with small lines and a polysilicon emitter structure are used in practical processes. [0004] figure 1 It is a schematic cross-sectional structure diagram of a transistor. The transistor includes a collector...

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Problems solved by technology

[0017] 1. There are many layers of photolithography: the production of the concentrated base region requires a separate photolithography layer process (step 2 above), and the process cost is relatively high;

[0018] 2. The width of the concentrated base region of the transistor must be greater than or equal to the width of the contact hole. In the above traditional method, the production of the concentrated base region and the contact hole is realized through different photoresist layers, and there must be a gap between different photoresist layers. There is a certain amount of alignment deviation. In order to ensure that the contact hole does not deviate from the area where the concentrated base region is located in the case of lithographic alignment deviation, it is necessary to make the width of the concentrated base region wider than the contact hole during chip design. Width is large enough (as in step 6 above Figure 7 d1 shown in ), this practice leads to larger chip area and higher cost

Because the photoresist layer in the concentrated base region is completed before the photoresist layer in the emission region, but because the photoresist layer in the concentrated base region is only implanted and doped in the preset area, it does not include the process steps for making step-shaped alignment marks. , so it is impossible to reserve and make alignment marks in the photoresist layer of the concentrated base area, that is to say, the photolithography of the emission area must be aligned with the alignment marks reserved in the photoresist layer of the active area to achieve alignment (with the photoresist layer of the concentrated base area Layers are not aligned and aligned)

[0020] Since the alignment deviation between layers of this indirect alignment is more difficult to control than that of direct alignment, in order to ensure that a safe distance is maintained between the emission region and the concentrated base region in the event of a large alignment deviation (to ensure that the two are not short-circuited), the set distance between the emission region and the concentrated base region must be sufficiently large during chip design, which leads to a larger chip area and higher cost

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