Time delay-based double-track pre-charge logic NAND gate circuit and Time delay-based double-track pre-charge logic exclusive or gate circuit

Abstract

The invention discloses a time delay-based double-track pre-charge logic NAND gate circuit and a time delay-based double-track pre-charge logic exclusive or gate circuit. By transforming positions of PMOS (P-channel metal oxide semiconductor) transistors or NMOS (N-channel metal oxide semiconductor) transistors in the time delay-based double-track pre-charge logic NAND gate circuit and the time delay-based double-track pre-charge logic exclusive or gate circuit in the prior art and increasing or decreasing the PMOS transistors or the NMOS transistors, the improvement of the NAND gate circuit and the exclusive or gate circuit is realized; the improved NAND gate circuit and the improved exclusive or gate circuit area capable of realizing more balanced power consumption, faster speed and lower power consumption, and can better resist differential power attack.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, and more specifically to a delay-based dual-rail precharge logic NAND circuit and an exclusive OR gate circuit. Background technique [0002] With the development of informatization and information industry, VLSI and computer technology are widely used in various fields of society. A large number of confidential systems have been established on the basis of the information industry, and the security of information systems has become a key issue that governments and various large organizations must pay attention to. Information security refers to the protection of software and hardware systems based on information systems and the data stored in the systems from being stolen, changed or even destroyed by the outside world. [0003] All information technology operations, including information encryption, are realized on the corresponding physical basis, but these physical founda...

AI Technical Summary

Problems solved by technology

[0013] However, such a circuit still has certain problems that lead to unbalanced power consumption. Figure 1e Take the NAND gate precharge stage of the circuit shown as an example to simulate, and the waveform diagram is as follows Figure 1k shown

It can be seen from the figure that the upper jump edge of the dual-rail signal input of the previous stage is later than the CLK signal for a certain period of time. During this period, the evaluation PMOS transistor still maintains the connection between the power supply and the intermediate node, while the NMOS precharge tube from the intermediate node to the ground is also turned on, thus creating a short circuit from supply to ground

Images