FPGA-based (field programmable gate array-based) embedded dual-core relay protecting system

A relay protection and embedded technology, applied in the field of embedded dual-core relay protection system, can solve problems such as inability to flexibly adapt to new and customized requirements, many core platform devices, and risk of chip production stoppage, so as to meet diversification and customization Performance requirements, flexible design, and low power consumption

Inactive Publication Date: 2015-06-10
NANJING DAQO AUTOMATION TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is: in view of the existing low-voltage microcomputer relay protection and automation device core platform devices with many devices, low integration, inability to flexibly adapt to new needs and customization needs, and the risk of production stoppage of chips used, the present invention The invention provides an FPGA-based embedded dual-core relay protection system to solve the above problems

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  • FPGA-based (field programmable gate array-based) embedded dual-core relay protecting system
  • FPGA-based (field programmable gate array-based) embedded dual-core relay protecting system
  • FPGA-based (field programmable gate array-based) embedded dual-core relay protecting system

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Embodiment Construction

[0017] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention. On the contrary, the embodiments of the present invention include all changes, modifications and equivalents coming within the spirit and scope of the appended claims.

[0018] In the description of the present invention, it should be understood that the terms "first", "second" and so on are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance. In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "connected" and "connect...

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Abstract

The invention provides an FPGA-based embedded dual-core relay protecting system. The FPGA-based embedded dual-core relay protecting system comprises a first NIOS II soft-core processor, a second NIOS II soft-core processor, an Avalon bus module and a mailbox module. The mailbox module is connected with the first NIOS II soft-core processor, the second NIOS II soft-core processor and the Avalon bus module. The FPGA-based embedded dual-core relay protecting system integrates the digital system onto one chip and accordingly is high in function density, small in size, low in power consumption and high in reliability; compared with a special ASIC (application specific integrated circuit), FPGA is low in cost and flexible in design and is the development tendency of integrated circuit design of future microcomputer relay protecting products; the FPGA-based embedded dual-core relay protecting system comprises data collection, logic processing and a variety of peripheral systems and can meet the requirements of hardware interfaces on diversification and customization.

Description

technical field [0001] The invention relates to the technical field of medium and low voltage microcomputer relay protection, in particular to an FPGA-based embedded dual-core relay protection system. Background technique [0002] At present, in the design of the product platform of low-voltage automation equipment in the power system, 90% of the products use special ASIC chips such as single-chip microcomputers, ARM or DSP. The performance of the whole machine system is greatly restricted due to the limitation of line delay, as well as its own size and weight, and the product MTBF (mean time between failure) value is low. With the continuous proposal and development of various complex algorithms in the power system and the new progress of communication technology, the performance of the traditional dedicated ASIC chip processor is challenged, and it is no longer good to rely solely on improving the clock frequency, data throughput and other indicators. To meet the need...

Claims

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Application Information

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IPC IPC(8): G05B19/042H02J13/00
CPCG05B19/0421Y02B90/20Y04S20/00
Inventor 吴参林陈栩李进张官勇吴军黄小波唐亮任宝军
Owner NANJING DAQO AUTOMATION TECH
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