Transistor forming method

Abstract

The invention provides a transistor forming method. The method includes forming a first false grid layer, a sacrificial layer and a second false grid layer on a substrate from bottom to top; forming a side wall on the side wall of a false grid, and obtaining a false grid structure comprising the false grid and the side wall; forming a source region and a leak region in the substrate; forming an interlayer medium layer exposing the surface of the false grid structure; allowing the sacrificial layer to serve as an etching stop layer, and removing the second false grid layer of the false grid structure by dry etching; removing the sacrificial layer; removing the first false grid layer by wet etching, and forming an opening; forming a metal grid electrode structure in the opening. The method has the advantages that the influence of the substrate during false grid removal is small, and the quality of a formed transistor is improved.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular to a method for forming a transistor. Background technique [0002] In the high-K dielectric / metal gate-last engineering of transistors, the gate-last process is generally used to form the metal gate. According to the existing gate-last process, a dummy gate structure is first formed, and then the dummy gate is removed, and a metal gate is formed in the opening created by removing the dummy gate. The feature sizes of various semiconductors manufactured by the current process are very small, and it is quite difficult to completely remove the dummy gate in such a small dummy gate structure. In the prior art, dry etching and wet etching are generally used to remove the dummy gate. [0003] However, the dry etching and wet etching used to remove the dummy gates have the following problems. Because in the wafer, the height of the dummy gates is different in the area where the dummy...

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Problems solved by technology

[0005] After dry etching the dummy gate 02 (06), the thickness of the remaining dummy gate 06 is different from that of the remaining dummy gate 02, resulting in wet etching of the remaining dummy gate 02 (06), such as figure 2 As shown, the thicker residual dummy gate 06 still remains, and the thinner residual dummy gate 02 is etched clean, but the dummy gate dielectric layer 03 and the substrate 01 under the thinner residual dummy gate 02 are subjected to wet etching. Corrosion effect and damage, thus affecting the performance of the transistor

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