Forming method of metal grid electrode

Abstract

A forming method of a metal grid electrode comprises the following steps: providing a semiconductor substrate, forming a pseudo grid electrode on the surface of the substrate, forming an interlayer dielectric layer on the substrate, allowing the top of the interlayer dielectric layer to level with the top of the pseudo grid electrode; utilizing an epitaxial growth to form a first sacrificial layer at least covering the top of the pseudo grid electrode; forming a second sacrificial layer on the interlayer dielectric layer, allowing the top of the second sacrificial layer to level with the top of the first sacrificial layer; removing the first sacrificial layer, forming an opening inside the second sacrificial layer, and exposing the bottom of the opening outside the top of the pseudo grid electrode; removing the pseudo grid electrode after removing the first sacrificial layer, and forming a grid electrode groove inside the interlayer dielectric layer; removing the second sacrificial layer, and forming the metal grid electrode by filling a metal layer inside the grid electrode groove. By the forming method of the metal grid electrode, the interlayer dielectric layer can be well protected from being damaged during the processing of removing the pseudo grid electrode, without reducing the depth of the grid electrode groove, accordingly the height of the subsequently formed metal grid electrode is not reduced, thereby increasing the performance of a subsequently formed device.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a metal gate. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is getting smaller and smaller. In the case of continuous shrinking of the feature size of MOS transistors, in order to reduce the parasitic capacitance of the gate of the MOS transistor and increase the speed of the device, the metal gate is introduced into the MOS transistor. [0003] Figure 1 to Figure 4 It is a schematic cross-sectional structure diagram of a method for forming a metal gate in the prior art. [0004] refer to figure 1 A semiconductor substrate 100 is provided, and a dummy gate 101 is formed on the substrate 100, and the material of the dummy gate is polysilicon. Next, a silicon oxide layer 102 covering the substrate 100 and the dummy gate 101 is formed, and the top of the silicon...

AI Technical Summary

Problems solved by technology

[0009] The problem solved by the present invention is that the performance of the metal grid formed by the method of the prior art is not good, and in severe cases, the metal grid cannot work normally

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