EEPROM memory device and preparation method thereof

Abstract

The invention relates to an EEPROM memory device and a preparation method thereof. The method comprises: providing a semiconductor substrate, which is provided with a gate of a high-voltage transistor and a floating gate of a memory device; depositing a gate dielectric layer on the gate of the high-voltage transistor and the floating gate; depositing a control gate material layer on the gate dielectric layer; etching the control gate material layer and the gate dielectric layer, so that a control gate is formed above the floating gate, and meanwhile, a first interval wall formed by the control gate material layer is arranged on the side wall of the gate of the high-voltage transistor; and forming a second interval wall on the first interval wall of the gate of the high-voltage transistor and the side wall of the control gate. The method has the following advantages that: (1) no other technology window is sacrificed in the method, and no extra production cost is additionally added; and (2) technical margin is added and further enables the size of the device to be smaller.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular, the invention relates to an EEPROM storage device and a preparation method. Background technique [0002] Electrically Erasable Programmable Read-Only Memory (EEPROM, Electrically Erasable Programmable Read-Only Memory) is a memory chip that does not lose data after power failure; it can erase existing information on a computer or a dedicated device and reprogram it. EEPROM is a non-volatile memory, and flash EEPROM among them is developing rapidly. EEPROM is more complex than DRAM, so it is difficult to improve the integration of EEPROM. [0003] The information-storing portion of an EEPROM memory cell is like a normally-off or normally-on transistor that, when the floating gate is charged, holds charge or blocks the flow of electrons from the control gate to the silicon; charging is applied to the control gate by grounding the source / drain. Voltage to complete; apply a reverse vol...

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Problems solved by technology

[0008] The first such as Figure 1b-1c As shown, after forming the gate 10 and the control gate 20 of the high voltage transistor, an additional oxide layer 105 is deposited on the gate 10 and the control gate 20 of the high voltage transistor, by adding additional oxide material layer 105 to increase the distance between the drain region and the gate, but the method will cause a process margin (marginal) for the self-parallel silicide barrier (SAB) process and the contact hole formation process, and the gate of the high-voltage transistor 10 and the control gate 20 will cause damage to the active area during gate etch

[0009] The second method as Figure 1d As shown, by forming a self-aligned silicide barrier layer 106 on both sides of the gate structure, and then performing source-drain implantation to increase the distance between the source-drain region and the gate, but the method leads to the size of the device increase, and since the source-drain region and the gate structure are not self-aligned structures, more process margin (marginal) needs to be added to solve this problem

[0010] Therefore, in the prior art, in order to improve the breakdown voltage of HV MOS in EEPROM, various methods have been tried, but each method has different disadvantages, such as causing complicated process or causing other damage to the device, etc.

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