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Memory and its driving circuit

A driving circuit and memory technology, which is applied in the field of semiconductors, can solve the problems of weakened driving ability of transistors, large substrate area, poor working state of driving circuits, etc., and achieve the effects of avoiding peak effects, meeting design requirements, and meeting small chip areas

Active Publication Date: 2019-03-29
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the above-mentioned transistors have a large substrate area and have relatively large parasitic loads. Therefore, in the driving circuit of the prior art, the charging and discharging process of the nodes (V11, V12) is easily affected by the parasitic loads and power supply. Influenced by the level, especially when the transistor is in the boundary condition (such as the density of the memory storage array becomes higher and the power supply voltage is lower), the driving ability of the transistor will be weakened accordingly, causing the driving circuit to work poorly, and the driving circuit cannot provide the corresponding bit. line and word line provide accurate operating voltage

Method used

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  • Memory and its driving circuit

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Embodiment Construction

[0059] In order to make the objectives, features, and effects of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0060] In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, so the present invention is not limited by the specific embodiments disclosed below.

[0061] Such as image 3 The driving circuit 2 of the memory includes: a level shift unit 200 and a substrate bias unit 201.

[0062] The level shift unit 200 includes a first node 202 suitable for inputting an access level Vv, a second node 203 suitable for inputting a substrate bias level Vb, and a third node 204 suitable for outputting a driving level Vs. The third node 204 is connected to the external device 205 of the driving ...

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Abstract

The present invention relates to a memory and a driving circuit thereof. The driving circuit comprises a level shifting unit and a substrate bias unit, wherein the level shifting unit comprises a first node for inputting an access level, a second node for inputting a substrate bias level, and a third node for outputting a driving level, the third node is connected to the word line or bit line in the memory, the substrate bias unit is suitable for providing the substrate bias level, the substrate bias level is less than the access level, and the memory comprises the driving circuit and a memory array. With the memory and the driving circuit of the present invention, the driving capability of the memory driving circuit can be improved.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a memory and its driving circuit. Background technique [0002] In the information age, information storage is one of the most important technical content in information technology. DRAM, EEPROM, flash memory and other memories are being used more and more widely. [0003] In order to achieve information access, such as reading or programming information, the memory needs to switch between different levels to obtain the required operating voltage: for example, in different operating modes of the memory, the drive circuit of the memory needs Provide different access voltages to the bit line and word line for the target memory cell. For example, in a read operation, the drive circuit needs to load a read voltage of about 2V on the selected bit line, while in a programming operation, the drive circuit needs A programming voltage of 10V is applied to the selected bit line t...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/06
Inventor 權彞振倪昊郑大燮金凤吉
Owner SEMICON MFG INT (SHANGHAI) CORP