Method for cleaning bonding pads

A pad and cleaning solution technology, which is applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of wire bonding failure, poor pad tensile strength and joint strength uniformity, and easy corrosion of pads and other issues to achieve the effect of improving tensile strength and joint strength, optimizing electrical conductivity and reliability, and preventing corrosion
CN104900481AActive Publication Date: 2015-09-09SEMICON MFG INT (SHANGHAI) CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SEMICON MFG INT (SHANGHAI) CORP
Publication Date
2015-09-09

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Abstract

Provided is a method for cleaning bonding pads. The method comprises: providing a substrate on which an interconnection line layer is formed, wherein bonding pads are formed on the surface of the interconnection line layer and passivation layers are formed on the surfaces of the bonding pads; removing the passivation layers on the surfaces of the bonding pads by etching until the surfaces of the bonding pads are exposed and halogen family ions are left on the surfaces of the bonding pads; and performing acidic cleaning on the bonding pads in order to remove the halogen family ions left on the surfaces of the bonding pads, wherein cleaning liquid used by the acidic cleaning is chromium phosphate solution. The method cleans the bonding pads with acidic cleanout liquid, effectively removes the halogen family ions left on the surfaces of the bonding pads, prevents the bonding pads from corroding, and improves the tensile strength and bonding intensity of the bonding pads so as to improve the conductivity and the reliability of a semiconductor device.
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Description

technical field

[0001] The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for cleaning pads. Background technique

[0002] As the manufacture of integrated circuits develops towards Ultra Large-Scale Integration (ULSI: Ultra Large-Scale Integration), the circuit density on the chip is getting higher and higher, and the number of components on the chip is increasing, and the surface of the chip can no longer provide enough area to Make the required interconnect structure (Interconnect). For this reason, a design method for multilayer interconnect structures with more than two layers is proposed. The design method forms grooves or through holes by etching the interlayer dielectric layer, and fills the grooves and through holes with conductive material to realize multi-layer electrical interconnection in the chip. After forming the interconnection structure, in order to realize the electrical connection between the c...

Claims

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