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Semiconductor device

A semiconductor and device technology, applied in the field of semiconductor devices, can solve the problems of large discrete resistance, inability to obtain withstand voltage, and inability to obtain epitaxial wafers, etc., to achieve the effect of suppressing the reduction in withstand voltage

Inactive Publication Date: 2015-09-09
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Wafers formed by the CZ method may have large dispersion in the in-plane specific resistance, and the target withstand voltage may not be obtained.
[0005] On the other hand, in the case of epitaxial wafers, multiple films are formed under different conditions in the same film formation apparatus, so it is difficult to control the impurity concentration, so there is also a possibility that an epitaxial wafer with the target withstand voltage cannot be obtained. sex

Method used

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  • Semiconductor device
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Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach

[0022] figure 1 is a schematic cross-sectional view showing the semiconductor device according to the first embodiment.

[0023] The semiconductor device 1 is a zener diode including a cathode electrode 10 as a lower electrode and an anode electrode 11 as an upper electrode.

[0024] On the cathode electrode 10 is provided with n ++ type sixth semiconductor region 20 . The sixth semiconductor region 20 is provided between the first semiconductor region 30 and the second semiconductor region 40 and the cathode electrode 10 . In addition, between the sixth semiconductor region 20 and the anode electrode 11, n - type of the first semiconductor region 30 .

[0025] set n + The second semiconductor region 40 is shaped so that it is located between the anode electrode 11 and the cathode electrode 10 and is adjacent to the first semiconductor region 30 . An n-type impurity element (such as phosphorus (P), arsenic (As), etc.) is introduced into the second semiconductor region 40...

no. 2 approach

[0067] Figure 5 is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0068] In the semiconductor device 2 , the third semiconductor region 50 is provided between the anode electrode 11 and the first semiconductor region 30 and the second semiconductor region 40 . That is, a part of the third semiconductor region 50 is exposed from the second semiconductor region 40 .

[0069] Here, the junction withstand voltage V of the second semiconductor region 40 and the third semiconductor region 50 23 , the junction withstand voltage V of the end portion 40e of the second semiconductor region 40 and the third semiconductor region 50 2e3 , the end portion 50e of the third semiconductor region 50 and the junction withstand voltage V of the first semiconductor region 30 2e3 The relationship between the junction withstand voltage V 23 designed to withstand a voltage higher than the second junction V 2e3 and the third junction withstand ...

no. 3 approach

[0072] Figure 6 is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0073] In the semiconductor device 3 , the end portion 50 e of the third semiconductor region 50 in the portion other than the surface 50 u on the anode electrode 11 side of the third semiconductor region 50 is surrounded by the fourth semiconductor region 60 . In addition, the portion other than the surface 60 u on the side of the anode electrode 11 of the fourth semiconductor region 60 is surrounded by the first semiconductor region 30 .

[0074] In the semiconductor device 3 , the end 50 e of the third semiconductor region 50 is surrounded by the fourth semiconductor region 60 , and thus the withstand voltage of the end 50 e of the third semiconductor region 50 becomes higher than that of the semiconductor device 2 .

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Abstract

A semiconductor device in an embodiment includes a first semiconductor region of a first conductivity type on a cathode electrode and a second semiconductor region of the first conductivity type between an anode electrode and the cathode electrode and in direct contact with the first semiconductor region. A first conductivity type dopant concentration of the second semiconductor region is higher than a first conductivity type dopant concentration of the first semiconductor region. A third semiconductor region of a second conductivity type is between the anode electrode and the second semiconductor region and in direct contact with the second semiconductor region. A fourth semiconductor region is in direct contact with the second semiconductor region and a portion of the third semiconductor region.

Description

technical field [0001] This application is based on and claims the benefit of the prior Japanese Patent Application No. 2014-043303 filed on Mar. 5, 2014, the entire contents of which are hereby incorporated by reference. [0002] The embodiments described herein relate generally to a semiconductor device. Background technique [0003] Diodes include ordinary pn diodes and Zener diodes utilizing breakdown current. Zener diodes generally have high-concentration regions and low-concentration regions. In order to obtain a predetermined withstand voltage, it is necessary to balance the junction formation of the high-concentration regions and low-concentration regions. Here, as the portion corresponding to the low-concentration region, a green wafer or an epitaxial wafer is used. [0004] Generally, a green wafer is formed by the CZ method (Czochralski Czochralski growth method), and a wafer having a predetermined withstand voltage is only a part of an ingot. A wafer formed by...

Claims

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Application Information

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IPC IPC(8): H01L29/861
CPCH01L29/8611H01L29/0619H01L29/36H01L29/66128
Inventor 杉田尚正
Owner KK TOSHIBA