A solid-state memory based on isolated memory array structure
A solid-state memory and storage array technology, applied in static memory, read-only memory, information storage, etc., can solve problems such as poor uniformity and stability of the process, hybrid crosstalk of semiconductor storage arrays, etc., to reduce integration, Effects of improved reading and writing accuracy and high photolithography alignment accuracy
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[0033] The embodiment of the present invention takes the MTJ array in MRAM as an example, and the materials selected for each layer are as follows Figure 5 Shown: Ta / Cu / Ta for the bottom electrode of the first layer; CoFeB / MgO / CoFeB for the functional layer of the second layer; Ta / Cu for the top electrode of the third layer.
[0034] The preparation method of the solid-state memory provided by the embodiment of the present invention includes the following steps:
[0035] (1) Substrate preparation: choose 4-inch thermal silicon oxide as the substrate material, and there is a layer of SiO with a thickness of 200nm on the surface of the silicon wafer 2 . Cut a 4-inch silicon wafer into a square centimeter substrate, and then ultrasonically clean it with acetone, alcohol and distilled water to obtain a clean substrate;
[0036] (2) Bottom electrode preparation: The electrode pattern is obtained on the cleaned substrate by photolithography and development, and then the electrode...
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