Hybrid interconnection structure for network-on-chip, network node encoding method and hybrid routing algorithm thereof

Abstract

The invention relates to a hybrid interconnection structure for a network-on-chip. The hybrid interconnection structure comprises a global network and a plurality of local networks, wherein the global network is of a binary tree structure consisting of a plurality of network nodes, and each local network is of a two-dimensional Mesh structure consisting of a plurality of network nodes, and a central node of the global network is connected with the network nodes on the global network. In the hybrid interconnection structure provided by the invention, the global network adopts the binary tree structure, each local network adopts the two-dimensional Mesh structure, and a matched network node encoding method and a hybrid routing algorithm are designed, so that data flow between global and local can be balanced, an average path distance between the local nodes can be reduced, and a network diameter is reduced, to improve the average transmission delay of the network and the network data throughput and effectively save the connecting line resources at the same time, and thus more network nodes can be added on the basis of the same connecting line resource.

Description

technical field [0001] The invention belongs to the technical field of on-chip network interconnection, and in particular relates to a hybrid interconnection structure for on-chip network, its network node coding method and its hybrid routing algorithm. Background technique [0002] With the rapid development of semiconductor process technology, microelectronics technology is rapidly changing from integrated circuit design to system chip design. However, with the continuous development of process technology, there are some problems related to the characteristics of SoC (system-on-chip), and such problems are difficult to solve under the traditional architecture of SoC. Based on this situation, the concept of network on chip (NoC) was proposed around 1999. The core idea is that the computing unit and the communication architecture are separated from each other, and the communication part draws on the computer network technology and transplants it into the integrated circuit ...

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Problems solved by technology

The disadvantages of this structural design are: symmetry can easily cause congestion and hotspots in the central area, resulting in unbalanced network load distribution; its edge nodes are relatively closed, and long-distance multi-hop communication between remote nodes is likely to cause delays. In terms of network architecture, consideration must be given Average path distance, scalability, number of nodes, network diameter, etc. of the topology

[0006] In practical applications, the communication frequency between each node of the on-chip network is different, and the communication between local cores is often more frequent. The above-mentioned single topological structures cannot take this difference into consideration. Difficult to meet real needs

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