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Low-temperature polysilicon array substrate and manufacturing method thereof

A low-temperature polysilicon and array substrate technology, which is applied in the manufacture of semiconductor/solid-state devices, instruments, semiconductor devices, etc., can solve problems affecting the quality of LTPS array substrates, damage to the gate insulation film, and high energy consumption, etc., to reduce peeling Difficulty, reduced energy, and reduced curing effects

Active Publication Date: 2019-01-29
WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the above-mentioned doping process, high-energy ion implantation is required, which not only consumes a lot of energy, but also causes damage to the quality of the gate insulating film because the ions pass through the gate insulating film, thereby affecting the quality of the LTPS array substrate. quality

Method used

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  • Low-temperature polysilicon array substrate and manufacturing method thereof
  • Low-temperature polysilicon array substrate and manufacturing method thereof
  • Low-temperature polysilicon array substrate and manufacturing method thereof

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Experimental program
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Embodiment 1

[0058] see figure 1 , which is a schematic flow chart showing the basic flow of the manufacturing method of the low-temperature polysilicon array substrate in the embodiment of the present invention. In this embodiment, the PMOS type thin film transistor and the NMOS type thin film transistor will be prepared

[0059] In step S101 , a PMOS thin film transistor region and an NMOS thin film transistor region are formed on a glass substrate.

[0060] Such as Figure 2A As shown, this step specifically includes:

[0061] (1) Deposit a light-shielding layer on the glass substrate 100, and perform etching to form a light-shielding layer pattern 200;

[0062] (2) sequentially forming a buffer layer 300 and an amorphous silicon layer on the light-shielding layer pattern 200;

[0063](3) An amorphous silicon layer is deposited, and crystallization and etching are performed on the amorphous silicon layer to form the PMOS thin film transistor region 400A and the NMOS thin film transi...

Embodiment 2

[0092] image 3 It is a block diagram of the low-temperature polysilicon array substrate in Embodiment 2 of the present invention. The low temperature polysilicon array substrate includes: a glass substrate 100 , a light-shielding layer pattern 200 , a buffer layer 300 , a polysilicon layer, and a gate insulating layer 500 .

[0093] The light-shielding layer patterns 200 , including the P-type light-shielding layer and the N-type light-shielding layer, are all deposited on the glass substrate 100 .

[0094] The buffer layer 300 is deposited on the light-shielding layer pattern 200 .

[0095] A polysilicon layer deposited on the buffer layer 300, comprising:

[0096] The PMOS thin film transistor region 400A, the boron heavily doped region 410A formed of high concentration boron in the channel formed around the PMOS thin film transistor region 400A; and

[0097] The NMOS thin film transistor region 400B, the low doped region 420B formed of low concentration phosphorus, and ...

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Abstract

The invention provides a low temperature poly-silicon array substrate and a manufacturing method therefor. The manufacturing method comprises the steps of: depositing a shade layer, etching a first shade pattern; depositing a noncrystalline silicon layer, performing crystallization treatment and etching treatment on the noncrystalline silicon layer to form a PMOS (positive channel metal oxide) thin film transistor region; coating first photoresist on the PMOS thin film transistor region to form shade channels on the noncrystalline silicon layer, and implanting high-concentration of boron ions in the PMOS thin film transistor region except the shade channels to form a boron heavily doped region, wherein the high-concentration of boron ions refer to that the concentration of the boron ions is greater than 1*10<13> pieces / cm<3>; and separately depositing a grid insulating film, grid metal, a common electrode, a passivation protection layer and a pixel electrode to form the low temperature poly-silicon array substrate. According to the preparation method, ions at the predetermined concentrations are implanted before the film formation of the grid insulating film to form the heavily doped region so as to form the corresponding ohmic contact, so that damage on the grid insulating film can be avoided, and the yield of the array substrate is effectively improved.

Description

technical field [0001] The invention relates to the technical field of liquid crystal display, in particular to a low-temperature polysilicon array substrate and a manufacturing method thereof. Background technique [0002] Low temperature polysilicon (LTPS for short), because of its high electron mobility, can effectively reduce the device area of ​​a thin film transistor (Thin Film Transistor, TFT for short), thereby increasing the aperture ratio of a pixel. [0003] However, due to the complexity of the LTPS process, especially the complementary metal oxide (Complementary Metal Oxide Semiconductor, CMOS) process, heavy phosphorus doping and boron heavy doping are required to form good metal-semiconductor characteristics. [0004] The traditional processing method is to carry out the low doping of the low-doped drain (Lightly doped Drain, referred to as LDD) and the heavy-duty of the positive channel metal oxide (Positive Channel Metal Oxide Semiconductor, referred to as P...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/77H01L21/266H01L27/12G02F1/1333
CPCG02F1/1333H01L21/26506H01L21/266H01L21/77
Inventor 刘元甫
Owner WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
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