Configurable protocol conversion state machine circuit structure and protocol configuration method

Abstract

The invention particularly relates to a configurable protocol conversion state machine circuit structure and a protocol configuration method. The configurable protocol conversion state machine circuit structure comprises a flash storer, a global reset control module and a protocol conversion state machine. The protocol conversion state machine comprises a register, a state coding module, a state matching module and a state decoding module. The register, the state coding module and the state decoding module are all connected to the state matching module. According to the configurable protocol conversion state machine circuit structure and the protocol configuration method, the chip protocol conversion is realized, so that risks in chip design can be well controlled; verification requirement on protocol details is lowered, so that the whole chip design process is faster, demand on verification resources is lowered accordingly, the circuit structure is simplified, overall, design difficulty of the whole chip system is lowered, and development time is remarkably shortened.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a configurable protocol conversion state machine circuit structure and a protocol configuration method. Background technique [0002] With the continuous development of the server application field, the application requirements of high-end servers have entered an important stage. The realization of complex architecture supports high-end server systems to achieve high performance indicators, high security, high availability, and high reliability. This requires a network control chip to control the multi-processor system, so that the internal message transmission of the system can be efficient, reliable, safe and stable. For the realization of this kind of control chip, the circuit realization of the protocol state transition table is the core of this chip system. In this case, the completeness of the protocol and the complex implementability are the keys to the success of th...

AI Technical Summary

Problems solved by technology

However, this method has great limitations. Limited by the resources and speed of the FPGA itself, it is difficult to completely transplant and maintain the consistency of the huge chip system. The verification of the circuit can only be partial and targeted, rather than comprehensive. Verification of azimuth without dead angle

At the same time, due to the relationship of FPGA speed, it can only verify the working conditions of the system in a slow environment, and it is not a completely consistent verification with the actual chip working at high speed.

For simulation and system-level verification, due to the limitation of simulation speed, the coverage of system verification within the limited design verification time is always an order of magnitude gap with FPGA, and it is difficult to fully and completely verify all circuit designs.

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