Digital signal edge delay correction system and method

Abstract

The present invention discloses a digital signal edge delay correction system and method. The system provided by the invention is in the circuit of a digital communication receiving end and allows the main control chip of the receiving end to comprise a rising edge collection module, a falling edge collection module, a high-frequency counter module, a frame synchronizing signal detection module and a delay correction module through adoption of a logic circuit, a programmable logic device or a software programming method, so that the changing of a high-level holding time and a low-level holding time cased by inconsistent rising edge delay and the falling edge delay generated during level signals passing through a relay or an isolation circuit in the process of digital communication process. The digital signal edge delay correction system and method are able to recover the level holding time distortion of system hardware in the process of digital signal transmission, are universally used in various digital level signal transmission occasions, and are able to decrease the requirement of the system for the hardware transmission speed and reduce the hardware cost and the design difficulty.

Description

technical field [0001] The invention relates to the field of digital signal processing, in particular to a digital signal edge delay correction system and method. Background technique [0002] In digital signal communication, due to the hardware characteristics of the isolation circuit or relay circuit, when the level signal passes through the relay or isolation circuit during the communication process, the delay of the rising edge and the delay of the falling edge will be inconsistent, making the signal high voltage The flat sustain time and the low level sustain time change, resulting in signal distortion. [0003] Taking the NPN triode drive circuit as an example, currently in the industry, acceleration capacitors are generally connected in parallel at both ends of the base resistor to increase the charging speed of the triode and speed up the rising edge speed; a diode is connected between the base and the collector to prevent the triode from entering the saturation regi...

AI Technical Summary

Problems solved by technology

[0002] In digital signal communication, due to the hardware characteristics of the isolation circuit or relay circuit, when the level signal passes through the relay or isolation circuit during the communication process, the delay of the rising edge and the delay of the falling edge will be inconsistent, making the signal high voltage The flat sustain time and low level sustain time change, which leads to signal distortion

[0003] Taking the NPN triode drive circuit as an example, currently in the industry, acceleration capacitors are generally connected in parallel at both ends of the base resistor to increase the charging speed of the triode and speed up the rising edge speed; a diode is connected between the base and the collector to prevent the triode from entering the saturation region. thus speeding up the falling edge

[0004] However, the effect of this method is limited by the correct selection of the capacitive reactance of the accelerating capacitor and the impedance of the resistor, and it can only improve the delay but cannot completely repair it. This distortion occurs in space-ratio-sensitive application scenarios

Moreover, this method is designed for the physical characteristics of triodes, and cannot solve the distortion that occurs in the application scenarios where non-triode devices constitute isolation circuits or relay circuits.

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