Digital signal edge delay correction system and method

A digital signal and edge technology, applied in the field of digital signal edge delay correction system, can solve the problems of signal distortion, speed up the rising edge speed, increase the charging speed of triode, etc., to repair distortion, reduce complexity, and reduce hardware transmission speed requirements Effect

Active Publication Date: 2016-05-04
GUANGZHOU LONGEST SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In digital signal communication, due to the hardware characteristics of the isolation circuit or relay circuit, when the level signal passes through the relay or isolation circuit during the communication process, the delay of the rising edge and the delay of the falling edge will be inconsistent, making the signal high voltage The flat sustain time and low level sustain time change, which leads to signal distortion
[0003] Taking the NPN triode drive circuit as an example, currently in the industry, acceleration capacitors are generally connected in parallel at both ends of the base resistor to increase the charging speed of the triode and speed up the rising edge s...

Method used

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  • Digital signal edge delay correction system and method
  • Digital signal edge delay correction system and method
  • Digital signal edge delay correction system and method

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Embodiment 1

[0043] Such as figure 2 As shown, the digital signal edge delay correction system of this embodiment adopts FPGA as the main control chip of the receiving end, and the FPGA includes a rising edge acquisition module, a falling edge acquisition module, a counter a, a timer b, and a frame synchronization signal detection module, Data selector, XOR gate, comparator, subtractor, delayer.

[0044] The system uses non-return-to-zero code to transmit data, the level change represents 1, and the level remains unchanged represents 0. The system clock adopts 38.4MHz, the signal frequency is 4.8MHz (bit rate 9.6Mbps), and the pulse width is 1.5 times as stated in the transmission protocol. The pulse corresponds to a frequency of 3.2MHz (1 / 4.8MHz*1.5=1 / 3.2MHz). The frame synchronization header of the data consists of a 3.2MHz half-wave (1 / 3.2MHz*1 / 2*1000=156.25ns), a 4.8MHz full-wave (1 / 4.8MHz*1000=208.33ns), a 3.2MHz A special sequence composed of half waves, the receiving end recogniz...

Embodiment 2

[0053] Such as figure 2 As shown, the digital signal edge delay correction system of this embodiment adopts FPGA as the main control chip of the receiving end, and the FPGA includes a rising edge acquisition module, a falling edge acquisition module, a counter a, a timer b, and a frame synchronization signal detection module, Data selector, XOR gate, comparator, subtractor, delayer.

[0054] The system uses non-return-to-zero code to transmit data, the level change represents 1, and the level remains unchanged represents 0. The system clock adopts 153.6MHz, the signal frequency is 4.8MHz (bit rate 9.6Mbps), and the pulse width is 1.5 times as stated in the transmission protocol. The pulse corresponds to a frequency of 3.2MHz (1 / 4.8MHz*1.5=1 / 3.2MHz). The frame synchronization header of the data consists of a 3.2MHz half-wave (1 / 3.2MHz*1 / 2*1000=156.25ns), a 4.8MHz full-wave (1 / 4.8MHz*1000=208.33ns), a 3.2MHz A special sequence composed of half waves, the receiving end recogni...

Embodiment 3

[0063] Such as figure 2 As shown, the digital signal edge delay correction system of this embodiment adopts FPGA as the main control chip of the receiving end, and the FPGA includes a rising edge acquisition module, a falling edge acquisition module, a counter a, a timer b, and a frame synchronization signal detection module, Data selector, XOR gate, comparator, subtractor, delayer.

[0064] The system uses non-return-to-zero code to transmit data, the level change represents 1, and the level remains unchanged represents 0. The system clock adopts 38.4MHz, the signal frequency is 4.8MHz (bit rate 9.6Mbps), and the transmission protocol is 0.5 times the pulse width. The pulse corresponds to a frequency of 9.6MHz (1 / 4.8MHz*0.5=1 / 9.6MHz). The frame synchronization header of the data consists of a 9.6MHz half-wave (1 / 9.6MHz*1 / 2*1000=52.08ns), a 4.8MHz full-wave (1 / 4.8MHz*1000=208.33ns), a 9.6MHz A special sequence composed of half waves, the receiving end recognizes the identit...

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Abstract

The present invention discloses a digital signal edge delay correction system and method. The system provided by the invention is in the circuit of a digital communication receiving end and allows the main control chip of the receiving end to comprise a rising edge collection module, a falling edge collection module, a high-frequency counter module, a frame synchronizing signal detection module and a delay correction module through adoption of a logic circuit, a programmable logic device or a software programming method, so that the changing of a high-level holding time and a low-level holding time cased by inconsistent rising edge delay and the falling edge delay generated during level signals passing through a relay or an isolation circuit in the process of digital communication process. The digital signal edge delay correction system and method are able to recover the level holding time distortion of system hardware in the process of digital signal transmission, are universally used in various digital level signal transmission occasions, and are able to decrease the requirement of the system for the hardware transmission speed and reduce the hardware cost and the design difficulty.

Description

technical field [0001] The invention relates to the field of digital signal processing, in particular to a digital signal edge delay correction system and method. Background technique [0002] In digital signal communication, due to the hardware characteristics of the isolation circuit or relay circuit, when the level signal passes through the relay or isolation circuit during the communication process, the delay of the rising edge and the delay of the falling edge will be inconsistent, making the signal high voltage The flat sustain time and the low level sustain time change, resulting in signal distortion. [0003] Taking the NPN triode drive circuit as an example, currently in the industry, acceleration capacitors are generally connected in parallel at both ends of the base resistor to increase the charging speed of the triode and speed up the rising edge speed; a diode is connected between the base and the collector to prevent the triode from entering the saturation regi...

Claims

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Application Information

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IPC IPC(8): G05B19/042
CPCG05B19/0423G05B2219/25249
Inventor 柒拾陆钟相燚
Owner GUANGZHOU LONGEST SCI & TECH
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